Rainbow Electronics AT84AD001B User Manual
Page 13
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13
AT84AD001B
2153C–BDC–04/04
Figure 6. 1:2 DMUX Mode, Clock I = ADC I, Clock I = ADC Q
CLKOI
(= CLKI/4)
CLKI
CLKOI
(= CLKI/2)
VIN
TA
N
N + 1
N + 2
N + 3
Pipeline delay = 4 clock cycles
TDO
TD2
DOIA[0:7]
NI - 2
NI - 4
NI
DOIB[0:7]
Pipeline delay = 3 clock cycles
TDO
NI - 3
NI - 1
NI +1
Address: D7 D6 D5 D4 D3 D2 D1 D0
1 0 X X 1 X 0 0
NQ - 4
NQ - 2
NQ
NQ - 3
NQ - 1
NQ +1
DOQA[0:7]
DOQB[0:7]
CLKOQ is high impedance
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