Rainbow Electronics DS2182A - Manual (Page 16)

DS2182A
041995 16/22
RBV OUTPUT
The bipolar violation output transitions high when the
accused bit emerges at RSER. RBV goes low at the
next bit time if no additional violations are detected.
RFER OUTPUT
The receive frame error output transitions high at the F-
bit time and is held high for two bit periods when a frame
bit error occurs. In 193S, framing FT and FS patterns
are tested. The FPS pattern is tested in 193E framing.
Additionally, in 193E framing, RFER reports CRC6 code
word errors by a low-high-low transition (one bit period-
wide) one-half RCLK period before a low-high transition
on RMSYNC (see Figure 17).
RESET
A high-low transition on RST clears all registers and
forces an immediate resync when RST returns high.
RST must be held low on system power-up to insure
proper initialization of the counters and registers. Fol-
lowing reset, the host processor should restore all con-
trol modes by writing appropriate registers with control
data.
ALARM OUTPUT TIMING Figure 17
RCLK
RFSYNC
RMSYNC
RFER
RBV
RCL
RLOS
NOTES:
1. RFER transitions high during F-bit time if received framing pattern bit is in error. (Frame 12 F-bits in 193S are
ignored if RCR2.3 = 1.) Also, in 193E, RFER transitions high 1/2 bit-time before rising edge of RMSYNC to
indicate a CRC6 error for the previous multiframe.
2. RBV indicates received bipolar violation and transitions high when accused bit emerges from RSER. If B8ZS
is enabled, RBV will not report the zero replacement code.
3. RCL transitions high when 192 consecutive bits are 0; RCL transitions low upon reception of 12.5% ones
density.
4. RLOS transitions high during F-bit time that caused an OOF event if auto-resync is enabled (RCR1.1 = 0).
Resync also occurs when loss of carrier is detected (RCL = 1) if RCR1.7 = 0. When RCR1.1 = 1, RLOS re-
mains low until resync occurs, regardless of OOF or carrier loss flags. In this situation, resync is initiated
only when RCR1.0 transitions low-to-high or the RST pin transitions high-low-high.