Rainbow Electronics DS1616 - Manual (Page 18)

DS1616
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These registers provide the most recently acquired ADC inputs. For the ADC channels that are enabled
with the CS[1-3] bits in the Control 2 register set to 1. Otherwise, the value in the corresponding Current
ADC Data [1-3] register will be all 0s and not reported by the Read Data command. It contains either the
most recently measured sample from automatic datalogging or it contains data that was acquired in
response to a user’s instruction for an immediate ADC conversion. When the DS1616 is not on a
mission, an immediate measurement is acquired by issuing the Read Data command with CSx set to a 1.
After issuing the Read Data command, the value in this register is valid only if the Data Ready (DR) bit
in the Status 2 register is a logic 1.
ADC DATA-HIGH THRESHOLD REGISTERS [1-3]
MSb LSb
AH7 AH6 AH5 AH4 AH3 AH2 AH1 AH0
These registers determines the high threshold for interrupt generation from the three muxed ADC inputs.
If the data is greater than or equal to the value in the corresponding register, an interrupt will be activated
if the Data High Interrupt Enable (AHIE) bit is set to a logic 1.
ADC DATA-LOW THRESHOLD REGISTERS [1-3]
MSb LSb
AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
These registers determines the low threshold for interrupt generation from the three muxed ADC inputs.
If the data is less than or equal to the value in the corresponding register, an interrupt will be activated if
the Data Low Interrupt Enable (ALIE) bit is set to a logic 1.
CONTROL 2 REGISTER
MSb LSb
0 CS0 CS1 CS2 CS3 ALIE AHIE 0
CSx - Channel Select [0-3] - The value of these bits determines which channels are enabled. A 1 in the
CSx bit enables the channel for data collection, recording and reporting. A 0 in the CSx bit disables the
channel so data will not be taken, recorded, or reported. This causes a common problem in retrieving
data, if the CSx bit is set to 0, the datalog and histogram data will not be downloaded from the DS1616.
ALIE - ADC Data Low Interrupt Enable - When set to a logic 1, this bit permits the ADC Data Low Flag
[1-3] (ALFx[1-3]) in the Status 2 register to assert INT . When the ALIE bit is set to logic 0, the ALF bit
does not initiate the INT signal.
AHIE - ADC Data High Interrupt Enable - When set to a logic 1, this bit permits the ADC Data High
Flag [1-3] (AHFx[1-3]) in the Status 2 register to assert INT . When the AHIE bit is set to logic 0, the
AHF bit does not initiate the INT signal.