Rainbow Electronics ADC12D040 - Manual (Page 4)

Pin Descriptions and Equivalent Circuits
Pin No. Symbol Equivalent Circuit Description
ANALOG I/O
15
2
V
IN
A+
V
IN
B+
Non-Inverting analog signal Inputs. With a 2.0V reference the
full-scale input signal level is 2.0 V
P-P
on each pin of the input
pair, centered on a common V
CM
.
16
1
V
IN
A−
V
IN
B−
Inverting analog signal Input. With a 2.0V reference the
full-scale input signal level is 2.0 V
P-P
on each pin of the input
pair, centered on a common V
CM
. These (-) input pins may be
connected to a common V
CM
for single-ended operation, but
a differential input signal is required for best performance.
7 V
REF
Reference input. This pin should be bypassed to AGND with
a 0.1 µF monolithic capacitor when external reference is
used. V
REF
is 2.0V nominal and should be between 1.0V to
2.4V.
11 INT/EXT REF
V
REF
select pin. With a logic low at this pin the internal 2.0V
reference is selected. With a logic high on this pin an external
reference voltage must be applied to V
REF
input pin 7.
13
5
V
RP
A
V
RP
B
These pins are high impedance reference bypass pins only.
Connect a 0.1 µF capacitor from each of these pins to AGND.
DO NOT LOAD these pins.
14
4
V
RM
A
V
RM
B
12
6
V
RN
A
V
RN
B
DIGITAL I/O
60 CLK
Digital clock input. The range of frequencies for this input is
100 kHz to 55 MHz (typical) with guaranteed performance at
40 MHz. The input is sampled on the rising edge of this input.
22
41
OEA
OEB
OEA and OEB are the output enable pins that, when low,
enables their respective TRI-STATE ® data output pins. When
either of these pins is high, the corresponding outputs are in a
high impedance state.
59 PD
PD is the Power Down input pin. When high, this input puts
the converter into the power down mode. When this pin is
low, the converter is in the active mode.
21 OF
Output Format pin. A logic low on this pin causes output data
to be in offset binary format. A logic high on this pin causes
the output data to be in 2’s complement format.
ADC12D040
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