Rainbow Electronics DS1202S - Manual (Page 9)

DS1202, DS1202S
032697 9/11
10. I
CC2
is specified with RST, I/O, and SCLK open. The clock halt flag must be set to logic one (oscillator disabled).
11. At power–up, RST must be at a logic 0 until V
CC
y 2 volts. Also, SCLK must be at a logic 0 when RST is driven
to a logic one state.
12. If t
CH
exceeds 100 ms with RST in a logic one state, then I
CC
may briefly exceed I
CC
specification.
DS1202 SERIAL TIMEKEEPER 8–PIN DIP
C
1
A
B
H
J
K
G
E
F
4
8 5
A IN. 0.360 0.400
MM
B IN. 0.240 0.260
MM
C IN. 0.120 0.140
MM
D IN. 0.300 0.325
MM
E IN. 0.015 0.040
MM
F IN. 0.110 0.140
MM
G IN. 0.090 0.110
MM
H IN. 0.320 0.370
MM
J IN. 0.008 0.012
MM
K IN. 0.015 0.021
MM
8–PIN PKG
D
DIM MIN MAX