Rainbow Electronics ATAR862-3 - Manual (Page 70)

70
ATAR862-3
4556B–4BMCU–02/03
Figure 68. Example of 8-bit Synchronous Receive Operation
9-bit Shift Mode (MCL) In the 9-bit shift mode, the SSI is able to handle the MCL protocol described below. It
always operates as an MCL master device, i.e., SC is always generated and output by
the SSI. Both the MCL start and stop conditions are automatically generated whenever
the SSI is activated or deactivated by the SIR-bit. In accordance with the MCL protocol,
the output data is always changed in the clock low phase and shifted in on the high
phase.
Before activating the SSI (SIR = 0) and commencing an MCL dialog, the appropriate
data direction for the first word must be set using the SDD control bit. The state of this
bit controls the direction of the data port (BP43 or MCL_SD). Once started, the 8 data
bits are, depending on the selected direction, either clocked into or out of the shift regis-
ter. During the 9th clock period, the port direction is automatically switched over so that
the corresponding acknowledge bit can be shifted out or read in. In transmit mode, the
acknowledge bit received from the device is captured in the SSI Status Register (TACK)
where it can be read by the controller. In receive mode, the state of the acknowledge bit
to be returned to the device is predetermined by the SSI Status Register (RACK).
Changing the directional mode (TX/RX) should not be performed during the transfer of
an MCL telegram. One should wait until the end of the telegram which can be detected
using the SSI interrupt (IFN = 1) or by interrogating the ACT status.
Once started, a 9-bit telegram will always run to completion and will not be prematurely
terminated by the SIR bit. So, if the SIR-bit is set to "1" in telegram, the SSI will complete
the current transfer and terminate the dialog with an MCL stop condition.
4 3 2 1 0 7 6 5 4 3 2 1 0
msb lsb
rx data 1 rx data 2 rx data 3
msb lsb msb lsb
Read SRB
(rx data 2) Read SRB
(rx data 3) Read SRB
(rx data 1)
SC
SD
SIR
SRDY
Interrupt
(IFN = 0)
Interrupt
(IFN = 1)
ACT
7 6 5 4 3 2 1 0 7 6 5 7 6 5 4