Rainbow Electronics MAX1243 - Manual (Page 4)

MAX1242/MAX1243
+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8
4 _______________________________________________________________________________________
TIMING CHARACTERISTICS
(V DD = +2.7V to +5.25V, circuit of Figure 9, T A = T MIN to T MAX , unless otherwise noted.)
Note 1: Tested at V DD = +2.7V.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offset have been calibrated.
Note 3: Offset nulled.
Note 4: Sample tested to 0.1% AQL.
Note 5: External load should not change during conversion for specified accuracy.
Note 6: Guaranteed by design. Not subject to production testing.
Note 7: Measured as [V FS (V DD(min) ) - V FS (V DD(max) )].
Note 8: To guarantee acquisition time, t ACQ is the maximum time the device takes to acquire the signal, and is also the minimum
time needed for the signal to be acquired.
DOUT DOUT
6k
DGND
C
LOAD
= 50pF C
LOAD = 50pF
6k
DGND
+2.7V
b) High-Z to V
OL
and V
OH
to V
OL
a) High-Z to V
OH
and V
OL
to V
OH
DOUT DOUT
6k
DGND
C
LOAD = 50pF
C
LOAD
= 50pF
6k
DGND
+2.7V
b) V
OL
to High-Z a) V
OH to High-Z
Figure 1. Load Circuits for DOUT Enable Time
Figure 2. Load Circuits for DOUT Disable Time
MAX124_ _M
MAX124_ _C/E
Figure 1, C LOAD = 50pF
Figure 1,
C
LOAD = 50pF
CS = V
DD (Note 8)
Figure 2, C LOAD = 50pF
CONDITIONS
ns 240 t DV
CS Fall to Output Enable
ns
20 200
t DO
µs 1.5 t
ACQ
Acquisition Time
SCLK Fall to Output Data Valid
ns 240 t CS
CS Pulse Width
ns 0 t STR DOUT Rise to SCLK Rise (Note 6)
ns 50 t CS0 SCLK Low to CS Fall Setup Time
ns 240 t TR
CS Rise to Output Disable
MHz 0 2.1 f SCLK SCLK Clock Frequency
ns 200 t CH SCLK Pulse Width High
ns 200 t CL SCLK Pulse Width Low
UNITS MIN TYP MAX SYMBOL PARAMETER
20 240