Rainbow Electronics MAX1068 User Manual

Page 6

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MAX1067/MAX1068

Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters

6

_______________________________________________________________________________________

TIMING CHARACTERISTICS (Figures 1, 2, 8, and 16)

(AV

DD

= +4.75V to +5.25V, DV

DD

= +2.7V to +5.25V, f

SCLK

= 4.8MHz external clock (50% duty cycle), 24 clocks/conversion

(200ksps), external V

REF

= +4.096V, T

A

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at T

A

= +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Acquisition Time

t

ACQ

External clock (Note 6)

729

ns

SCLK to DOUT Valid

t

DO

C

DOUT

= 30pF

100

ns

CS Fall to DOUT Enable

t

DV

C

DOUT

= 30pF

100

ns

CS Rise to DOUT Disable

t

TR

C

DOUT

= 30pF

80

ns

CS Pulse Width

t

CSW

100

ns

SCLK rise

CS to SCLK Setup

t

CSS

SCLK fall (DSP)

100

ns

SCLK rise

CS to SCLK Hold

t

CSH

SCLK fall (DSP)

0

ns

Conversion

93

SCLK High Pulse Width

t

CH

Duty cycle 45% to 55%

Data transfer

93

ns

Conversion

93

SCLK Low Pulse Width

t

CL

Duty cycle 45% to 55%

Data transfer

93

ns

SCLK Period

t

CP

209

ns

SCLK rise

DIN to SCLK Setup

t

DS

SCLK fall (DSP)

100

ns

SCLK rise

DIN to SCLK Hold

t

DH

SCLK fall (DSP)

0

ns

CS Falling to DSPR Rising

t

DF

100

ns

DSPR to SCLK Falling Setup

t

FSS

100

ns

DSPR to SCLK Falling Hold

t

FSH

0

ns

Note 1: AV

DD

= DV

DD

= +5.0V.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been

calibrated.

Note 3: Offset and reference errors nulled.
Note 4: DC voltage applied to on channel, and a full-scale 1kHz sine wave applied to off channels.
Note 5: Conversion time is measured from the rising edge of the 8th external SCLK pulse to EOC transition minus t

ACQ

in 8-bit data-

transfer mode.

Note 6: See Figures 10 and 17.
Note 7: f

SCLK

= 4.8MHz, f

INTCLK

= 4.0MHz. Sample rate is calculated with the formula f

s

= n

1

(n

2

/ f

SCLK

+ n

3

/ f

INTCLK

)-1 where: n

1

= number of scans, n

2

= number of SCLK cycles, and n

3

= number of internal clock cycles (see Figures 11–14).

Note 8: Internal reference and buffer are left on between conversions.
Note 9: Defined as the change in the positive full scale caused by a ±5% variation in the nominal supply voltage.

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