Rainbow Electronics MAX1718 User Manual
Page 26
MAX1718
Notebook CPU Step-Down Controller for Intel
Mobile Voltage Positioning (IMVP-II)
26
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age rating rather than by capacitance value (this is true
of tantalums, OS-CONs, and other electrolytics).
When using low-capacity filter capacitors such as
ceramic or polymer types, capacitor size is usually
determined by the capacity needed to prevent V
SAG
and V
SOAR
from causing problems during load tran-
sients. Generally, once enough capacitance is added
to meet the overshoot requirement, undershoot at the
rising load edge is no longer a problem (see the V
SAG
equation in the Design Procedure section). The amount
of overshoot due to stored inductor energy can be cal-
culated as:
where I
PEAK
is the peak inductor current.
Output Capacitor Stability
Considerations
Stability is determined by the value of the ESR zero rela-
tive to the switching frequency. The voltage-positioned
circuit in this data sheet has the ESR zero frequency low-
ered due to the external resistor in series with the output
capacitor ESR, guaranteeing stability. For a voltage-posi-
tioned circuit, the minimum ESR requirement of the output
capacitor is reduced by the voltage-positioning resistor
value.
The boundary condition of instability is given by the fol-
lowing equation:
(R
ESR
+ R
DROOP
)
✕
C
OUT
≥ 1 / (2
✕
f
SW
)
where R
DROOP
is the effective value of the voltage-
positioning resistor (Figure 1, R8). For good phase mar-
gin, it is recommended to increase the equivalent RC
time constant by a factor of two. The standard applica-
tion circuit (Figure 1) operating at 300kHz with C
OUT
=
1320µF, R
ESR
= 2.5m
Ω, and R
DROOP
= 5m
Ω easily
meets this requirement. In some applications, the C
OUT
and R
DROOP
values are sufficient to guarantee stability
even if R
ESR
= 0.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output voltage ripple envelope for over-
shoot and ringing. Don’t allow more than one cycle of
ringing after the initial step-response under/overshoot.
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (I
RMS
) imposed by the switching currents
defined by the following equation:
For most applications, nontantalum chemistries (ceramic
or OS-CON) are preferred due to their resistance to
inrush surge currents typical of systems with a switch
or a connector in series with the battery. If the
MAX1718 is operated as the second stage of a two-
stage power-conversion system, tantalum input capaci-
tors are acceptable. In either configuration, choose an
input capacitor that exhibits less than +10°C tempera-
ture rise at the RMS input current for optimal circuit
longevity.
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
(>12A) when using high-voltage (>20V) AC adapters.
Low-current applications usually require less attention.
The high-side MOSFET must be able to dissipate the
resistive losses plus the switching losses at both
V
IN(MIN)
and V
IN(MAX)
. Calculate both of these sums.
Ideally, the losses at V
IN(MIN)
should be roughly equal
to the losses at V
IN(MAX)
, with lower losses in between.
If the losses at V
IN(MIN)
are significantly higher than the
losses at V
IN(MAX)
, consider increasing the size of Q1.
Conversely, if the losses at V
IN(MAX)
are significantly
higher than the losses at V
IN(MIN)
, consider reducing
the size of Q1. If V
IN
does not vary over a wide range,
the minimum power dissipation occurs where the resis-
tive losses equal the switching losses.
Choose a low-side MOSFET (Q2) that has the lowest
possible R
DS(ON)
, comes in a moderate-sized package
(i.e., two or more SO-8s, DPAKs or D
2
PAKs), and is rea-
sonably priced. Ensure that the MAX1718 DL gate dri-
ver can drive Q2; in other words, check that the dv/dt
caused by Q1 turning on does not pull up the Q2 gate
due to drain-to-gate capacitance, causing cross-con-
duction problems. Switching losses aren’t an issue for
the low-side MOSFET since it’s a zero-voltage switched
device when used in the buck topology.
MOSFET Power Dissipation
The high-side MOSFET power dissipation due to resis-
tance is:
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the R
DS(ON)
required to stay within package
PD Q
sistive
V
V
I
R
OUT
IN
LOAD
DS ON
(
Re
)
(
)
1
2
=
Ч
Ч
I
I
V
V
V
V
RMS
LOAD
OUT
IN
OUT
IN
=
−
(
)
V
L I
C
V
SOAR
PEAK
OUT
≈
Ч
Ч Ч
2
2