Timing characteristics (continued) – Rainbow Electronics MAX1402 User Manual
Page 8
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
8
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Note 19:
All input signals are specified with t
r
= t
f
= 5ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6V.
Note 20:
See Figure 4.
Note 21:
Timings shown in tables are for the case where SCLK idles high between accesses. The part may also be used with the
SCLK idling low between accesses, provided CS is toggled. In this case SCLK in the timing diagrams should be inverted
and the terms “SCLK Falling Edge” and “SCLK Rising Edge” exchanged in the specification tables. If CS is permanently
tied low, the part should only be operated with SCLK idling high between accesses.
Note 22:
CLKIN duty cycle range is 45% to 55%. CLKIN must be supplied whenever the MAX1402 is not in standby mode. If no
clock is present, the device can draw higher current than specified.
Note 23:
The MAX1402 is production tested with f
CLKIN
at 2.5MHz (1MHz for some I
DD
tests).
Note 24:
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
Note 25:
For read operations, SCLK active edge is falling edge of SCLK.
Note 26:
Derived from the time taken by the data output to change 0.5V when loaded with the circuit of Figure 1. The number is then
extrapolated back to remove effects of charging or discharging the 50pF capacitor. This ensures that the times quoted in
the timing characteristics are true bus-relinquish times and are independent of external bus loading capacitances.
Note 27:
INT returns high after the first read after an output update. The same data can be read again while INT is high, but be
careful not to allow subsequent reads to occur close to the next output update.
Note 28:
Auxiliary inputs DS0 and DS1 are latched on the first falling edge of SCLK during a data-read cycle.
SCLK High Pulse Width
t
16
100
ns
SCLK Low Pulse Width
t
17
100
ns
Data Valid to SCLK Rising Edge
Hold Time
t
15
0
ns
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
CS Falling Edge to SCLK Falling
Edge Setup Time
t
13
30
ns
Data Valid to SCLK Rising Edge
Setup Time
t
14
30
ns
CONDITIONS
TIMING CHARACTERISTICS (continued)
(V+ = +5V ±5%, V
DD
= +2.7V to +5.25V, AGND = DGND, f
CLKIN
= 2.4576MHz; input logic 0 = 0V; logic 1 = V
DD
, T
A
= T
MIN
to T
MAX
,
unless otherwise noted.) (Notes 19, 20, 21)
CS Rising Edge to SCLK Rising
Edge Hold Time
t
18
0
ns
DS0/DS1 to SCLK Falling Edge
Hold Time (Notes 21 & 28)
t
20
0
ns
DS0/DS1 to SCLK Falling Edge
Setup Time (Notes 21 & 28)
t
19
40
ns
800
µ
A
at V
DD
= +5V
100
µ
A
at V
DD
= +3.3V
TO
OUTPUT
PIN
50pF
200
µ
A
at V
DD
= +5V
100
µ
A
at V
DD
= +3.3V
Figure 1. Load Circuit for Bus-Relinquish Time and V
OL
and
V
OH
Levels
AUXILIARY DIGITAL INPUTS (DS0 and DS1)