Rainbow Electronics MAX1625 - Manual (Page 19)

MAX1624/MAX1625
High-Speed Step-Down Controllers with
Synchronous Rectification for CPU Power
______________________________________________________________________________________ 19
Compensating the Feedback Loop
The feedback loop needs proper compensation to pre-
vent excessive output ripple and poor efficiency
caused by instability. Compensation cancels unwanted
poles and zeros in the DC-DC converter’s transfer func-
tion that are due to the power-switching and filter ele-
ments with corresponding zeros and poles in the
feedback network. These compensation zeros and
poles are set by the compensation components CC1,
CC2, and RC1. The objective of compensation is to
ensure stability by ensuring that the DC-DC converter’s
phase shift is less than 180° by a safe margin, at the
frequency where the loop gain falls below unity.
One simple method for ensuring adequate phase mar-
gin is to place pole-zero pairs to approximate a single-
pole response with a -20dB/decade slope all the way to
unity-gain crossover (Figure 8). (Other compensation
schemes are possible.) The order of undesired poles
and zeros may differ from that shown in Figure 8,
depending on the characteristics of the load, output
filter capacitor, switching frequency, and inductor.
These procedures are guidelines only, and empirical
experimentation is needed to select the compensation
components’ final values.
Canceling the Sampling Pole
and Output Filter ESR Zero
Compensate the fast-voltage feedback loop by con-
necting a resistor and a capacitor in series from the
CC1 pin to AGND. The pole from CC1 can be set to
cancel the zero from the filter-capacitor ESR. Thus the
capacitor at CC1 should be as follows:
Resistor RC1 sets a zero that can be used to compen-
sate for the sampling pole generated by the switching
frequency. Set RC1 to the following:
The CC1 pin’s output resistance is 10k
Ω
. In the sam-
pling pole equation (Figure 8), D MAX is the maximum
duty cycle, or V
OUT
/ V
IN(MIN)
.
Setting the Dominant Pole
and Canceling the Load and Output Filter Pole
Compensate the slow-voltage feedback loop by adding
a ceramic capacitor from the CC2 pin to AGND. This is
an integrator loop used to cancel out the DC load-
regulation error. Selection of capacitor CC2 sets the
dominant pole and a compensation zero. The zero is
typically used to cancel the unwanted pole generated
by the load and output filter capacitor at the maximum
load current. Select CC2 to place the zero close to or
slightly lower than the frequency of the unwanted pole,
as follows:
The transconductance of the integrator amplifier at CC2
is 1mmho. The voltage swing at CC2 is internally
clamped around 2.4V to 3V minimum and 4V to V
CC
maximum to improve transient response times. CC2
can source and sink up to 100µA.
CC
mmho x C
x
V
I
OUT OUT
OUT MAX
2
1
4
( )
=
RC
V
V
f x CC
OUT
IN
OSC
1
1
2 1
=
+

 

CC
C x R
k
OUT ESR
1
10
=
Ω
FREQUENCY (LOG)
LOOP
GAIN
DOMINANT POLE
FROM INTEGRATOR
UNWANTED
POLE FROM
R
LOAD C OUT COMPENSATION ZERO
TO CANCEL POLE FROM
R
LOAD C OUT
COMPENSATION
POLE TO CANCEL
ZERO FROM
C
OUT R ESR
UNWANTED ZERO
FROM C
OUT R ESR
UNWANTED
SAMPLING POLE
COMPENSATION
ZERO TO CANCEL
SAMPLING POLE
DESIRED RESPONSE
2 π (RC1 x CC1)
2 π (10k Ω x CC1)
1
1
(1 + D MAX ) x π
f OSC(MIN)
2 π R ESR x C OUT
1
2 π R LOAD(MAX) x C OUT
1
2 π 50k Ω x CC2
1
1mmho
2 π x 4CC2
GAIN (dB LINEAR)
Figure 8. MAX1624/MAX1625 Bode Plot with Compensation
Poles and Zeros