Rainbow Electronics MAX1201 - Manual (Page 10)

M
A
X12
01
+5V Single-Supply, 2.2Msps, 14-Bit
Self-Calibrating ADC
10 ______________________________________________________________________________________
Analog Signal Conditioning
For single-ended inputs, the negative analog input pin
(INN) is tied to the common-mode voltage pin (CM),
and the positive analog input pin (INP) is connected to
the input signal. The common-mode voltage of INP
must be equal to the common-mode input. To take full
advantage of the ADC’s superior AC performance up to
Nyquist frequency, drive the chip with differential sig-
nals. While in communication systems the signals may
inherently be available in differential mode, medical
and/or other applications may only provide single-
ended inputs. In this case, convert the single-ended
signals into differential ones by using the circuit recom-
mended in Figure 5. Use low-noise, wideband ampli-
fiers, such as the MAX4108, to maintain the signal
purity over the full-power bandwidth of the MAX1201.
Lowpass or bandpass filters may be required to
improve the signal-to-noise-and-distortion ratio of the
incoming signal. For low-frequency signals (<100kHz),
active filters may be used. For higher frequencies, pas-
sive filters are more convenient.
Single-Ended to Differential
Conversion Using Transformers
An alternative single-ended to differential-ended con-
version method is a balun transformer such as the
CTX03-13675 from Coiltronics. An important benefit of
these transformers is their ability to level-shift a single-
ended signal, referred to ground on the primary side, to
optimum common-mode voltages on the secondary
side. At frequencies below 20kHz, the transformer core
begins to saturate, causing odd-order harmonics.
Clock Source Requirements
Pipelined ADCs typically need a 50% duty cycle clock.
To avoid this constraint, the MAX1201 provides a
divide-by-two circuit which relaxes this requirement.
The clock generator should be chosen commensurate
with the frequency range, amplitude and slew rate of
the signal source. If the slew rate of the input signal is
low, the jitter requirement on the clock is relaxed.
However, if the slew rate is high, the clock jitter needs
to be kept at a minimum. For a full-scale amplitude
input sine wave, the maximum possible SNR due com-
pletely to clock jitter is given by
For example, if f IN is 1MHz and
σ
JITTER is 10ps RMS,
then the SNR limit due to jitter is approximately 84dB.
Generating such a clock source requires a low-noise
comparator and a low-phase noise signal generator. The
clock circuit shown in Figure 6 is a possible solution.
SNR
1
2 MAX
IN JITTER
f
=
⋅ ⋅ ⋅ π σ
MAX4108
INP
INN
CM
V-
V+
IN
CM
V+
V-
MAX4108
Figure 5. A simple circuit generates differential signals from a
single-ended input referred to analog ground. The common-
mode voltage at INP and INN is the same as CM.
MAX961
CLK
V+
V+
0.1 µ F
0.1 µ F
0.1 µ F 1k
1k
CLK_IN
5k
Figure 6. Clock Generation Circuit Using Low-Noise Comparator