Electrical characteristics (continued) – Rainbow Electronics MAX3629 User Manual
Page 3
MAX3629
+3.3V, Low-Jitter, Precision Clock Generator
with Multiple Outputs
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +3.0V to +3.6V, T
A
= 0°C to +70°C, unless otherwise noted. Typical values are at V
DD
= +3.3V, T
A
= +25°C, unless otherwise
noted. When using X_IN, X_OUT input, no signal is applied at OSC_IN. When PLL is enabled, PLL_BP = high-Z or high. When PLL is
bypassed, PLL_BP = low.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INPUT SPECIFICATIONS (FSELA, FSELB,
PLL_BP Pins)
Input-Voltage High
V
IH
2.0
V
DD
V
Input-Voltage Low
V
IL
0
0.8
V
Input High Current
I
IH
V
IN
= V
DD
80
μA
Input Low Current
I
IL
V
IN
= 0V
-80
μA
LVCMOS/LVTTL INPUT SPECIFICATIONS (OSC_IN) (Note 6)
PLL
enabled
25
Input Clock Frequency
PLL bypassed
20
320
MHz
Input Amplitude Range
(Note 7)
1.2
3.6
V
Input High Current
I
IH
V
IN
= V
DD
80
μA
Input Low Current
I
IL
V
IN
= 0V
-80
μA
Reference Clock Duty Cycle
40
50
60
%
Input Capacitance
C
IN
1.5
pF
CLOCK OUTPUT AC SPECIFICATIONS
VCO
Center
Frequency
625 MHz
FSELA = GND
125
FSELA = V
DD
156.25
Output Frequency with PLL
Enabled (Q0)
FSELA = high-Z
312.5
MHz
FSELB = GND
125
FSELB = V
DD
156.25
Output Frequency with PLL
Enabled (Q1 to Q7)
FSELB = high-Z (Note 8)
312.5
MHz
LVDS outputs
20
320
Output Frequency with PLL
Disabled
LVCMOS outputs
20
160
MHz
12kHz to 20MHz,
PLL_BP = high (Note 9)
0.4
Integrated Phase Jitter at
125MHz/156.25MHz
RJ
RMS
12kHz to 20MHz,
PLL_BP = high-Z
(Note 10)
0.4
ps
RMS
LVDS
output
-55
Power-Supply Noise Rejection
(Note 11)
LVCMOS
output
-47
dBc
LVDS
output
9
Deterministic Jitter Due to
Supply Noise (Note 12)
LVCMOS
output
23
ps
P-P
Nonharmonic and Subharmonic
Spurs
(Note
13)
-73 dBc
f
=
100Hz
-116
f
=
1kHz
-124
f
=
10kHz
-127
f = 100kHz
-131
f
=
1MHz
-144
LVDS Clock Output SSB Phase
Noise at 125MHz (Note 14)
f
>
10MHz
-149
dBc/Hz