Design procedure – Rainbow Electronics MAX1885 User Manual

Page 25

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MAX1778/MAX1880–MAX1885

Quad-Output TFT LCD DC-DC

Converters with Buffer

______________________________________________________________________________________

25

where I

MAIN

includes the primary load current and the

input supply currents for the charge pumps (see
Charge-Pump Input Power and Efficiency
Considerations
), linear regulator, and VCOM buffer.

The linear regulator generates an output voltage by dis-
sipating power across an internal pass transistor, so
the power dissipation is simply the load current times
the input-to-output voltage differential:

When driving an external transistor, the internal linear
regulator provides the base drive current. Depending
on the external transistor’s current gain (

β) and the

maximum load current, the power dissipated by the
internal linear regulator may still be significant:

The charge pumps provide regulated output voltages
by dissipating power in the low-side N-channel MOS-
FET, so they could be modeled as linear regulators fol-
lowed by unregulated charge pumps. Therefore, their
power dissipation is similar to a linear regulator:

where N is the number of charge-pump stages, V

DIODE

is the diodes’ forward voltage, and V

SUPD

is the posi-

tive charge-pump diode supply (Figure 4).

The VCOM buffer’s power dissipation depends on the
capacitive load (C

LOAD

) being driven, the peak-to-

peak voltage change (V

P-P

) across the load, and the

load’s switching rate:

To find the total power dissipated in the device, the
power dissipated by each regulator and the buffer must
be added together:

The maximum allowed power dissipation is 975mW (24-
pin TSSOP) / 879mW (20-pin TSSOP) or:

P

MAX

= (T

J(MAX

) - T

A

) / (

θ

JB

+

θ

BA

)

where T

J

- T

A

is the temperature difference between

the controller’s junction and the surrounding air,

θ

JB

(or

θ

JC

) is the thermal resistance of the package to the

board, and

θ

BA

is the thermal resistance from the print-

ed circuit board to the surrounding air.

Design Procedure

Main Step-Up Converter

Output Voltage Selection

Adjust the output voltage by connecting a voltage-
divider from the output (VMAIN) to FB to GND (see
Typical Operating Circuit). Select R2 in the 10k

Ω to

50k

Ω range. Calculate R1 with the following equations:

R1 = R2 [(V

MAIN

/ V

REF

) - 1]

where V

REF

= 1.25V. V

MAIN

may range from V

IN

to 13V.

Inductor Selection

Inductor selection depends upon the minimum required
inductance value, saturation rating, series resistance, and
size. These factors influence the converter’s efficiency,
maximum output load capability, transient response time,
and output voltage ripple. For most applications, values
between 4.7µH and 22µH work best with the controller’s
switching frequency (Tables 1 and 2).

The inductor value depends on the maximum output
load the application must support, input voltage, output
voltage, and switching frequency. With high inductor
values, the MAX1778/MAX1880–MAX1885 source high-
er output currents, have less output ripple, and enter
continuous conduction operation with lighter loads;
however, the circuit’s transient response time is slower.
On the other hand, low-value inductors respond faster
to transients, remain in discontinuous conduction oper-
ation, and typically offer smaller physical size for a
given series resistance and current rating. The equa-
tions provided here include a constant LIR, which is the
ratio of the peak-to-peak AC inductor current to the
average DC inductor current. For a good compromise
between the size of the inductor, power loss, and out-
put voltage ripple, select an LIR of 0.3 to 0.5. The
inductance value is then given by:

L

V

V

V

V

I

f

LIR

MIN

IN MIN

MAIN

MAIN

IN MIN

MAIN MAX OSC

(

)

(

)

(

)

=















2

1

-

η

P

P

P

P

P

P

TOTAL

STEP UP

LDO INT

NEG

POS

BUF

(

)

=

+

+

+

+

-

P

V

C

f

V

BUF

P P LOAD LOAD SUPB

=

-

P

I

V

V

N

V

P

I

V

V

N

V

V

NEG

NEG

SUPN

DIODE

NEG

POS

POS

SUPP

DIODE

SUPD

POS

=

(

)

[

]

=

(

)

+

[

]

-

-

-

-

2

2

P

I

V

V

V

I

V

V

LDO INT

LDO

SUPL

LDO

LDOOUT

SUPL

LDOOUT

(

)

.

(

)

=

+

(

)

[

]

=

β

-

-

0 7

P

I

V

V

LDO INT

LDO

SUPL

LDO

(

)

(

)

=

-

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