Rainbow Electronics MAX1002 - Manual (Page 9)

Output Data Format
The conversion results are output on a dual 6-bit-wide
data bus. Data is latched into the ADC output latch fol-
lowing a pipeline delay of one clock cycle (Figure 8).
Output data is clocked out of the respective ADC’s data-
output pins (D_0 through D_5) on the rising edge of the
clock output (DCLK), with a DCLK-to-data propagation
delay (t
PD ) of 7.1ns. The MAX1002 outputs are TTL com-
patible.
Transfer Function
Figure 9 shows the MAX1002’s nominal transfer function.
Output coding is offset binary with 1LSB = FSR / 63.
MAX1002
Low-Power, 60Msps, Dual, 6-Bit ADC
_______________________________________________________________________________________ 9
Figure 9. Ideal Transfer Function
111111
OUTPUT CODE
111110
111101
100001
100000
011111
011110
000011
000010
000001
000000
-FSR
2
0
1LSB
INPUT VOLTAGE
FSR
2
(_IN+ to _IN-)
Figure 8. MAX1002 Timing Diagram
DATA OUT 1.4V DATA VALID N - 1 DATA VALID N
1.4V
50%
t SKEW
t
DCLK
t AP
t PD
TNK+
(INPUT CLOCK)
DCLK
ANALOG
INPUT
N
N + 1
N + 2