Rainbow Electronics MAX101А - Manual (Page 9)

MAX101A
500Msps, 8-Bit ADC with Track/Hold
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ADATA
BDATA
CLK
DCLK
t PD2
t PD2
N-1 N+3
N-2 N N+2
N–1 N N+1 N+2 +14 +15 +16 +17
0 1 7 8
N+1
NOTE: DATA ARBITRARY ON START-UP FOR SIDE A OR B, SEE INPUT CLOCK PHASING SECTION.
Figure 2. Output Timing, Clock to Data, Normal Mode (DIV10 = OPEN)
N+5
ADATA
BDATA
CLK
DCLK
NOTE: DATA ARBITRARY ON START-UP FOR SIDE A OR B, SEE INPUT CLOCK PHASING SECTION.
N
N N+1 N+2 N+3 +15 +16 +17
Figure 3. Output Timing, Test Mode (DIV10 = GND)