Rainbow Electronics MAX1541 User Manual
Page 41
A reasonable minimum value for h is 1.5, but adjusting
this up or down allows trade-offs between V
SAG
, output
capacitance, and minimum operating voltage. For a
given value of h, the minimum operating voltage can be
calculated as:
where V
DROP1
is the parasitic voltage drop in the
charge path (see the On-Time One-Shot section),
t
OFF(MIN)
is from the Electrical Characteristics, and K is
taken from Table 3. The absolute minimum input voltage
is calculated with h = 1.
If the calculated V
IN(MIN)
is greater than the required
minimum input voltage, then operating frequency must
be reduced or output capacitance added to obtain an
acceptable V
SAG
. If operation near dropout is anticipat-
ed, calculate V
SAG
to be sure of adequate transient
response.
Dropout Design Example
•
V
OUT2
= 2.5V
•
f
SW
= 355kHz
•
K = 3.0µs, worst-case K
MIN
= 3.3µs
•
t
OFF(MIN)
= 500ns
•
V
DROP1
= 100mV
•
h = 1.5
Calculating again with h = 1 and the typical K-factor
value (K = 3.3µs) gives the absolute limit of dropout:
Therefore, V
IN
must be greater than 3.06V, even with
very large output capacitance, and a practical input volt-
age with reasonable output capacitance would be 3.47V.
Multi-Output Voltage Settings
(MAX1541 OUT1 Only)
While the main MAX1541 controller (OUT1) is optimized
to work with applications that require two dynamic out-
put voltages, it can produce three or more output volt-
ages if required by using discrete logic or a DAC.
Figure 15 shows an application circuit providing four
voltage levels using discrete logic. Switching resistors
in and out of the resistor network changes the voltage
at REFIN1. An edge-detection circuit is added to gen-
erate a 1µs pulse on GATE to trigger the fault blanking
and forced-PWM operation. When using PWM mode
(SKIP = V
CC
or open) on the main controller, the edge-
detection circuit is only required if fault blanking is
enabled. Otherwise, leave OD unconnected.
Active Bus Termination
(MAX1541 OUT1 Only)
Active-bus-termination power supplies generate a volt-
age rail that tracks a set reference. They are required to
source and sink current. DDR memory architecture
requires active bus termination. In DDR memory archi-
tecture, the termination voltage is set at exactly half the
memory supply voltage. Configure the main MAX1541
controller (OUT1) to generate the termination voltage
using a resistive voltage-divider at REFIN1. In such an
application, the main MAX1541 controller (OUT1) must
be kept in PWM mode (SKIP = V
CC
or open) in order
for it to source and sink current. Figure 16 shows the
main MAX1541 controller configured as a DDR termina-
tion regulator. Connect GATE and FBLANK to GND
when unused.
V
V
V
ns
s
V
IN(MIN)
-
=
+
×
=
.
.
.
.
2 5
0 1
1
1 500
3 3
3 06
µ
V
V
V
ns
s
V
IN(MIN)
-
=
+
×
=
.
.
.
.
.
2 5
0 1
1
1 5 500
3 0
3 47
µ
V
V
V
h
t
K
IN(MIN)
OUT
DROP1
OFF(MIN)
-
=
+
×
1
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
______________________________________________________________________________________
41
Figure 15. Multi-Output Voltage Settings
MAX1541
REF
REFIN1
GND
GATE
R4
R3
A
C1
R2
R1
B
1000pF
1.5k
Ω
1000pF
1.5k
Ω