Communication Concepts EB104 Engineering Bulletin - Manual (Page 3)

ARCHIVE INFORMA
TION
ARCHIVE INFORMA
TION
EB104
3 RF Application Reports
b. a.
c. d.
C1
D1 R3
R4
RF
R1
C2
V+
R2
C1
D1
R3
R4
RF
R1
C2
V+
C1
D1
R3
RF
R1
C2
V+
R2
C1
D1 R3
R4
RF
R1
C2
V+
R2
Figure 3. Various Bias Configurations
The gate de-Qing in these circuits is done with R4. Circuit
“d” is another variation, where D1 is moved in series with
R1 eliminating R4. The value of R1 must be high to prevent
destruction from a drain-gate short. The common bias is
derived from IC1 (MC1723CP) which provides both line and
load regulation. The line voltage regulation is defeated when
the voltage to Pin 12 falls below 24 V, and the bias input
can be used for Automatic Level Control (ALC) shut-down
or linear ALC function. The regulator output voltage is
adjustable from 0.5 to 9.0 volts with R5, which can be
permanently set to 7.0 – 8.0 V. This voltage is also controlled
by the combination of R10 and R25. R25 is a thermistor,
and is tied to the heat sink for bias temperature
compensation.
In Figure 2, the input from T1 is fed to the gates through
C7 – C10 and R15 – R18. The input matching is initially done
at the high end of the band (30 MHz). In contrast to a bipolar
push-pull circuit, where the base-to-base impedance varies
with class of operation, the gate-to-gate impedance of a
common source FET circuit is always twice that from gate
to ground. In this case, where two FETs are in parallel on
each side, the gate-to-gate impedance equals the
gate-to-ground impedance of one device. From the Smith
chart information (Figure 4) this can be established as
3.45 ohms.
Chart Not Available Electronically
Figure 4. Series Equivalent Impedance