HP XC System 3.x Software - Manual (Page 96)

Viewing Itanium xperf (Enhanced) Statistics
Figure 1-2 (page 22) shows an xperf display for an Itanium system. By default, xperf displays
graphs with processor-dependent, enhanced statistics. The xperf utility displays graphs with
the following enhanced statistics for Itanium processors.
NOTE: The processor event names listed in this section are used for Itanium Processor 9000
series and may differ slightly from the event names used for other Itanium processor types.
CPU
Displays the following CPU utilization percentages from the /proc/stat file:
•
Idle : CPU utilization for idle cycles
• System : CPU utilization for system processes
• User : CPU utilization for user processes
Instructions
Displays the following instructions per cycle (IPC) statistics:
•
Raw : IA64_INST_RETIRED + PREDICATE_SQUASHED_RETIRED
• Effective : IA64_INST_RETIRED - NOPS_RETIRED
FPC
Displays the statistic Retired, which is the number of floating point operations retired per cycle
(FP_OPS_RETIRED).
Cycles
Displays the following statistics, per cycle:
• RSE Active : BE_RSE_BUBBLE
• D1TLB : BE_L1D_FPU_BUBBLE.L1D_TLB
• D2TLB : BE_L1D_FPU_BUBBLE.L1D_HPW
• Data Access : (BE_L1D_FPU_BUBBLE.L1D - BE_L1D_FPU_BUBBLE.L1D_HPW -
BE_L1D_FPU_BUBBLE.L1D_TLB) + (BE_EXE_BUBBLE.GRALL -
BE_EXE_BUBBLE.GRGR + BE_EXE_BUBBLE.FRALL)
• Score Board (stalls waiting for resources): BE_L1D_FPU_BUBBLE.FPU +
BE_EXE_BUBBLE.GRGR + BE_EXE_BUBBLE.ARCR_PR_CANCEL_BANK
• BE Flush : BE_FLUSH_BUBBLE.ALL
• Taken Branch : BACK_END_BUBBLE.FE * ((BE_LOST_BW_DUE_TO_FE.ALL -
(BE_LOST_BW_DUE_TO_FE.TLBMISS + BE_LOST_BW_DUE_TO_FE.IMISS)) /
BE_LOST_BW_DUE_TO_FE.ALL)
• Inst Access : BACK_END_BUBBLE.FE * ((BE_LOST_BW_DUE_TO_FE.TLBMISS +
BE_LOST_BW_DUE_TO_FE.IMISS ) / BE_LOST_BW_DUE_TO_FE.ALL)
• Execution : CPU_CYCLES - BACK_END_BUBBLE.ALL
Cache
Displays the following types of cache misses per second calculated from cache miss counts and
the time penalties for accessing different levels of cache memory:
•
L1icache misses : Level 1 instruction cache misses
• L1dcache misses : Level 1 data cache misses
• L2cache misses : Level 2 cache misses (single-core only)
• L2icache misses : Level 2 instruction cache misses (dual-core only)
• L2dcache misses : Level 2 data cache misses (dual-core only)
96 Using Xtools