MagTek SWIPE READERS WITH 3-TRACK - Manual (Page 11)

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SECTION 3. OPERATION
This section describes the SPI (Serial Peripheral Interface), the SPI bus interface timing, power
up messages and timeouts, card data transmission timeouts, and data output format. For a
description of abbreviations see Table 3-1 and Figure 3-1 below.
Table 3-1. Description of Terms
Term Description
DAV Data Valid (output)
CPHA Clock Phase
CPOL Clock Polarity
LSB Least Significant Bit
MSB Most Significant Bit
SCL Serial Clock (input)
SDA Serial Data (output)
SPI Serial Peripheral Interface
SPI
The SPI interface can be thought of as a variable-byte parallel to serial shift register. A variable
number of data bytes are transmitted serially in 8-bit groups in the order of MSB to LSB. Data
transfers occur when the DAV (Data Valid) status line is high.
For example, the bit transmission order for consecutive bytes A and B would be:
A(bit 7) A(bit 6) … A(bit 0) B(bit 7) B(bit 6) … B(bit 0)
Referring to Figure 3-1, the first data bit (MSB of the first byte to transmit) is set up prior to
DAV assertion. DAV is raised high by the reader and data on the SDA line is then clocked out
by the Host via the SCL line.
Data can be clocked into the Host on the rising edge of SCL or the Host can sample SDA while
the SCL clock line is high. When the SCL clock goes low, the reader will fetch the next bit to
place onto the SDA line.
After the last bit (LSB) of the last data byte is received by the Host, the reader will wait for the
Host to lower SCL. When SCL is returned low, the reader will set DAV low to indicate that all
data has been transmitted. The reader will remain in an idle state (with reduced current draw)
until a new card swipe occurs. The DAV line will then be reasserted when the reader has
collected the card data and is ready to transmit it to the Host.