Analog Devices MicroConverter ADuC832 User Manual

Page 2

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BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY

(not used)

(reserved)

SPICON

F8h

04h

F0h

00h

I2CCON

E8h

00h

ACC

E0h

00h

ADCCON2

D8h

00h

PSW

D0h

00h

T2CON

C8h

00h

WDCON

C0h

10h

B8h

00h

B0h

FFh

A8h

00h

A0h

FFh

SCON

98h

00h

90h

FFh

TCON

88h

00h

80h

FFh

DAC0L

F9h

00h

ADCOFSL

F1h

00h

ADCDA

D9h

00h

ECON

B9h

00h

IEIP2

A9h

A0h

SBUF

99h

00h

TMOD

89h

00h

81h

07h

DAC0H

00h

ADCOFSH

F2h

20h

ADCDA

DAh

00h

DMAL

D2h

00h

RCAP2L

CAh

00h

TL0

8Ah

00h

DPL

82h

00h

DAC1L

FBh

00h

ADCGAINL

F3h

00h

DMAH

D3h

00h

RCAP2H

CBh

00h

TL1

8Bh

00h

DPH

83h

00h

DAC1H

FCh

00h

ADCGAINH

F4h

00h

DMAP

D4h

00h

TL2

CCh

00h

ATA

BCh

00h

TH0

8Ch

00h

DPP

84h

00h

DACCON

FDh

04h

ADCCON3

F5h

00h

TH2

CDh

00h

ATA

BDh

00h

TH1

8Dh

00h

EADRL

C6h

00h

ATA

BEh

00h

SPIDA

F7h

00h

ADCCON1

EFh

00h

PSMCON

DFh

DEh

ATA

BFh

00h

PCON

87h

00h

SPR0

F8h

F0h

I2CI

E8h

E0h

CS0

D8h

D0h

CAP2

C8h

WDWR

C0h

PX0

B8h

RXD

B0h

EX0

A8h

A0h

98h

90h

IT0

88h

80h

SPR1

F9h

F1h

I2CTX

E9h

E1h

CS1

D9h

D1h

CNT2

C9h

WDE

C1h

PT0

B9h

TXD

B1h

ET0

A9h

A1h

99h

T2EX

91h

IE0

89h

81h

CPHA

F2h

I2CRS

EAh

E2h

CS2

DAh

D2h

TR2

CAh

WDS

C2h

PX1

BAh

INT0

B2h

EX1

AAh

A2h

RB8

9Ah

92h

IT1

8Ah

82h

CPOL

FBh

F3h

I2CM

EBh

E3h

CS3

DBh

RS0

D3h

EXEN2

CBh

WDIR

C3h

PT1

BBh

INT1

B3h

ET1

ABh

A3h

TB8

9Bh

93h

IE1

8Bh

83h

SPIM

FCh

F4h

MDI

ECh

E4h

SCONV

DCh

RS1

D4h

TCLK

CCh

C4h

BCh

B4h

ACh

A4h

REN

9Ch

94h

TR0

8Ch

84h

SPE

FDh

F5h

MCO

EDh

E5h

CCONV

DDh

D5h

RCLK

CDh

PRE1

C5h

PT2

BDh

B5h

ET2

ADh

A5h

SM2

9Dh

95h

TF0

8Dh

85h

WCOL

FEh

F6h

MDE

EEh

E6h

DMA

DEh

D6h

EXF2

CEh

PRE2

C6h

PADC

BEh

B6h

EADC

AEh

A6h

SM1

9Eh

96h

TR1

8Eh

86h

ISPI

FFh

F7h

MDO

EFh

E7h

ADCI

DFh

D7h

TF2

CFh

PRE3

C7h

PSI

BFh

B7h

AFh

A7h

SM0

9Fh

97h

TF1

8Fh

87h

SPR0

F8h

SPICON

F8h

04h

SPR1

F9h

mnemonic
reset value
address

mnemonic

address

reset value

these bits

this byte

are contained in

calibration coefficients are preconfigured at power-up to factory calibrated values

7Fh
...
30h
2Fh
2Eh
2Dh
2Ch
2Bh
2Ah
29h
28h
27h
26h
25h
24h
23h
22h
21h
20h
1Fh

1Eh

1Dh

1Ch

1Bh

1Ah

19h

18h

17h

16h

15h

14h

13h

12h

11h

10h

0Fh

0Eh

0Dh

0Ch

0Bh

0Ah

09h

08h

07h

06h

05h

04h

03h

02h

01h

00h

General Purpose

Area

Bit Addressable

Area

Register Bank 3

7Fh

7Eh

7Dh

7Ch

7Bh

7Ah

79h

78h

77h

76h

75h

74h

73h

72h

71h

70h

6Fh

6Eh

6Dh

6Ch

6Bh

6Ah

69h

68h

67h

66h

65h

64h

63h

62h

61h

60h

5Fh

5Eh

5Dh

5Ch

5Bh

5Ah

59h

58h

57h

56h

55h

54h

53h

52h

51h

50h

4Fh

4Eh

4Dh

4Ch

4Bh

4Ah

49h

48h

47h

46h

45h

44h

43h

42h

41h

40h

3Fh

3Eh

3Dh

3Ch

3Bh

3Ah

39h

38h

37h

36h

35h

34h

33h

32h

31h

30h

2Fh

2Eh

2Dh

2Ch

2Bh

2Ah

29h

28h

27h

26h

25h

24h

23h

22g

21h

20h

1Fh

1Eh

1Dh

1Ch

1Bh

1Ah

19h

18h

17h

16h

15h

14h

13h

12h

11g

10h

0Fh

0Eh

0Dh

0Ch

0Bh

0Ah

09h

08h

07h

06h

05h

04h

03h

02h

01h

00h

127
...
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

decimal address

HEX address

(bit addresses)

4K bytes

(1K pages)

data

Flash/EE

(accessible

through

SFRs)

CFG832.0=0

external

data

memory

(16M bytes

addressable)

addre

address

3FFh

000h

( page 0 )

( page 1023 )

Register Bank 2

Register Bank 1

Register Bank 0

CFG832.0=1

internal

data

memory

2K bytes

000h

FFFFFFh

7FFh

PLLCON

D7h

53h

CHIPID

C2h

2Xh

EADRH

C7h

00h

PWM0L

B1h

00h

PWM0H

B2h

00h

PWM1L

B3h

00h

PWM1H

B4h

00h

SPH

B7h

00h

CFG832

AFh

00h

PWMCON

AEh

00h

TIMECON

A1h

00h

HTHSEC

A2h

00h

SEC

A3h

00h

MIN

A4h

00h

HOUR

A5h

00h

INTV

A6h

00h

DPCON

A7h

00h

T3FD

9Dh

00h

T3CON

9Eh

00h

PRE0

I2CDA

9Ah

00h

I2CADD

9Bh

55h

SFR MAP & RESET VALUES

SFR DESCRIPTIONS

DATA MEMORY: RAM, SFRs, user Flash/EE (all read/write)

MAP KEY

DATA MEMORY SPACE

(read/write area)

LOWER RAM

SFR details

DACCON.7

ModeSelect (0=12bit, 1=8bit)

DACCON.6

DAC1 RangeSelect (0=V

REF

, 1=V

)

DACCON.5

DAC0 RangeSelect (0=V

REF

, 1=V

)

DACCON.4

Clear DAC1 (0=0V, 1=normal operation)

DACCON.3

Clear DAC0 (0=0V, 1=normal operation)

DACCON.2

SynchronousUpdate (1=asynchronous)

DACCON.1

PowerDown DAC1 (0=off, 1=on)

DACCON.0

PowerDown DAC0 (0=off, 1=on)

ADCCON3.7

busy indicator flag (0=ADC not active)

ADCCON3.6

gain calibration disable (0=gain cal enabled)

ADCCON3.5

number of averages selection bits:

ADCCON3.4

[15,1,31,63]

ADCCON3.3

cal clock divide select (0=ADCclk, 1=ADCclk/2)

ADCCON3.2

cal mode select (0=device, 1=system)

ADCCON3.1

cal type select (0=offset, 1=gain)

ADCCON3.0

start calibration bit, cleared by hardware

DACCON

DAC Control register

DAC1H

DAC1L

DAC1 data registers

ADCCON3

ADC Control register #3

ADCGAINH

ADC Gain

calibration coefficients

ADCGAINL
ADCOFSH
ADCOFSL

ADC Offset

calibration coefficients

auxiliary math register

ACC

Accumulator

PSMCON

Power Supply Monitor control register

PSMCON.6

PSM status bit (1=normal / 0=fault)

PSMCON.5

PSM interrupt bit

PSMCON.4

trip point select bits

PSMCON.3

[4.37V, 3.08V, 2.93V, 2.63V]

PSMCON.2

(this bit must contain zero)

PSMCON.1

(reserved)

PSMCON.0

PSM powerdown control (1=on / 0=off)

ADCDATAH

ADC Data registers

ADCDATAL
DMAP

DMAH

DMAL

DMA address pointer

carry flag

auxiliary carry flag

general purpose flag 0

RS1

RS0

active register bank = [0,1,2,3]

overflow flag

general purpose flag 1

parity of ACC

DAC0H

DAC0L

DAC0 data registers

PSW

Program Status Word

TH2,TL2

Timer2 register

RCAP2H,RCAP2L

Timer2 Reload/Capture

TF2

overflow flag

EXF2

external flag

RCLK

receive clock enable (0=Timer1 used for RxD clk)

TCLK

transmit clock enable (0=Timer1 used for TxD clk)

EXEN2

external enable (0=ignore T2EX, 1=cap/rld on T2EX)

TR2

run control (0=stop, 1=run)

CNT2

timer/counter select (0=timer, 1=counter)

CAP2

capture/reload select (0=reload, 1=capture)

T2CON

Timer2 Control register

PSI

priority of ISPI/I2CI (serial interface interrupt)

PADC

priority of ADCI (ADC interrupt)

PT2

priority of TF2/EXF2 (Timer2 overflow interrupt)

priority of RI/TI (serial port interrupt)

PT1

priority of TF1 (Timer1 overflow interrupt)

PX1

priority of IE1 (external interrupt 1)

PT0

priority of TF0 (Timer0 overflow interrupt)

PX0

priority of IE0 (external interrupt 0)

Interrupt Priority register

external data memory read strobe

external data memory write strobe

timer/counter 1 external input

timer/counter 0 external input

INT1

external interrupt 1

INT0

external interrupt 0

TxD

serial port transmit data line

RxD

serial port receive data line

Port3 register

enable inturrupts (0=all inturrupts disabled)

EADC

enable ADCI (ADC interrupt)

ET2

enable TF2/EXF2 (Timer2 overflow interrupt)

enable RI/TI (serial port interrupt)

ET1

enable TF1 (Timer1 overflow interrupt)

EX1

enable IE1 (external interrupt 1)

ET0

enable TF0 (Timer0 overflow interrupt)

EX0

enable IE0 (external interrupt 0)

Interrupt Enable register #1

Port2 register

(also A8-A15 & A16-A23)

SBUF

Serial port Buffer register

SM0

UART mode control bits baud rate:

SM1

00 - 8bit shift register - F

OSC

/12

01 - 8bit UART

- variable

10 - 9bit UART

- F

OSC

/64(x2)

11 - 9bit UART

- variable

SM2

in modes 2&3, enables multiprocessor communication

REN

receive enable control bit

TB8

in modes 2&3, 9th bit transmitted

RB8

in modes 2&3, 9th bit received

TItransmit interrupt flag

RIreceive interrupt flag

SCON

Serial communications Control register

T2EX

timer/counter 2 capture/reload trigger

timer/counter 2 external input

Port1 register (analog & digital inputs)

TH0,TL0

Timer0 registers

TH1,TL1

Timer1 registers

TMOD.3/.7

gate control bit (0=ignore INTx)

TMOD.2/.6

counter/timer select bit (0=timer)

TMOD.1/.5

timer mode selecton bits

TMOD.0/.4

[13bitT, 16bitT/C, 8bitT/Creload, 2x8bitT]

(upper nibble = Timer1, lower nibble = Timer0)

TMOD

Timer Mode register

TF1

Timer1 overflow flag (auto cleared on vector to ISR)

TR1

Timer1 run control (0=off, 1=run)

TF0

Timer0 overflow flag (auto cleared on vector to ISR)

TR0

Timer0 run control (0=off, 1=run)

IE1

external INT1 flag (auto cleared on vector to ISR)

IT1

IE1 type (0=level trig, 1=edge trig)

IE0

external INT0 flag (auto cleared on vector to ISR)

IT0

IE0 type (0=level trig, 1=edge trig)

TCON

Timer Control register

PCON.7 double baud rate control

PCON.4 ALE disable (0=normal, 1=forces ALE high)

PCON.3 general purpose flag

PCON.2 general purpose flag

PCON.1 power-down control bit (recoverable with hard reset)

PCON.0 idle-mode control (recoverable with enabled interrupt)

PCON

Power Control register

DPP

Data Pointer Page

DPH,DPL (DPTR)

Data Pointer

Stack Pointer

Port0 register

(also A0-A7 & D0-D7)

ADCCON1.7

ADC mode (0=off, 1=on)

ADCCON1.6

external Vref select bit (0=on-chip Vref)

ADCCON1.5

conversion time = 16 / ADCclk

ADCCON1.4

ADCclk = 16,777,216Hz / [8,4,16,32]

ADCCON1.3

acquisition time select bits

ADCCON1.2

acq time = [1,2,3,4] / ADCclk

ADCCON1.1

Timer2 convert enable

ADCCON1.0

external CONVST enable

ADCCON1

ADC Control register #1

ADCCON2

ADC Control register #2

ADCI

ADC interrupt flag

DMA

DMA mode enable

CCONV

continuous conversion enable bit

SCONV

single conversion start bit

CS3

input channel select bits:

CS2

0 - 7 = ADC0 - ADC7

CS1

8 = temperature sensor

CS0

9=DAC0, A=DAC1, B=AGND

PLLCON.7

oscillator powerdown control bit (0=XTAL on)

PLLCON.6

PLL lock indicator flag (0=out of lock)

PLLCON.5

(this bit must contain zero)

PLLCON.4

(this bit must contain zero)

PLLCON.3

fast interrupt control bit (0=normal)

PLLCON.2

3-bit clock divider value, CD (default=3):

PLLCON.1

PLLCON.0

PLLCON

PLL Control register

CORE

= 16,777,216Hz / 2

TIMECON.6 (this bit must contain 1)

TIMECON.5 INTVAL timebase select bits

TIMECON.4 [128th sec, seconds, minutes, hours]

TIMECON.3 single time interval control bit (0=reload&restart)

TIMECON.2 time interval interrupt bit, TII

TIMECON.1 time interval enable bit (0=disable&clear)

TIMECON.0 time clock enable bit (0=disable)

TIMECON

Time Interval Counter Control Register

HTHSEC

TIC Elapsed 128th Second Register

SEC

TIC Elapsed Seconds Register

MIN

TIC Elapsed Minutes Register

HOUR

TIC Elapsed Hours Register

INTVAL

TIC Interval Register

CFG832

ADuC832 Configuration Register

CFG832.7

extended stack-pointer enable (0=disable)

CFG832.6

PWM pins select (0=P2.6/P2.7,1=P3.4/P3.3)

CFG832.5

DAC output buffer bypass (0=buffer enabled)

CFG832.4

external clock select (0=internal clock)

CFG832.3

(this bit must contain 0)

CFG832.2

(this bit must contain 0)

CFG832.1

(this bit must contain 0)

CFG832.0

internal XRAM select (0=external XRAM)

EADRH

EADRL

Data Flash/EE address registers

EDATA1

EDATA2

EDATA3

EDATA4

Data Flash/EE data registers

01h READ page

02h PROGRAM page

04h VERIFY page

05h ERASE page

06h ERASE ALL

ECON

Data Flash/EE comand register

82h PROGRAM byte

0Fh EXIT ULOAD mode

F0h ENTER ULOAD mode

(all others reserved)

ISPI

SPI inturrupt (set at end of SPI transfer)

WCOL

write collision error flag

SPE

SPI enable (0=I2C enable, 1=SPI enable)

SPIM

master mode select (0=slave)

CPOL

clock polarity select (0=SCLK idles low)

CPHA

clock phase select (0=leading edge latch)

SPR1

SPI bitrate select bits

SPR0

bitrate = Fcore / [2,4,8,16] (slave: SPR0=SS)

SPICON

SPI Control register

SPIDAT

SPI Data register

PRE3

watchdog timeout selection bits

PRE2

0-7=[15.6,31.2,62.5,125,250,500,1000,2000]ms

PRE1

8=0ms (immediate reset)

PRE0

>8=reserved

WDIR

watchdog interrupt response bit

WDS

watchdog status flag (1 indicates watchdog timeout)

WDE

watchdog enable control (0=disabled)

WDWR

watchdog write enable bit (set to enable write)

WDCON

Watchdog Timer control register

IEIP2.6

priority of TII interrupt (time interval)

IEIP2.5

priority of PSMI interrupt (power supply monitor)

IEIP2.4

priority of ISPI interrupt (serial interface)

IEIP2.3

(this bit must contain zero)

IEIP2.2

enable TII interrupt (time interval)

IEIP2.1

enable PSMI (power supply monitor interrupt)

IEIP2.0

enable ISPI interrupt (serial interface)

IEIP2

Interrupt Enable/Priority register #2

CHIPID

Chip ID Register

(2X hex = ADuC832)

SPH

Stack Pointer High byte

PWMCON

PWM Control register

PWMCON.6 PWM mode bits [0=disabled, 1=single/var.res.,

PWMCON.5 2=twin/8bit, 3=twin/16bit, 4=dual/16bitNRZ,

PWMCON.4 5=dual/8bit, 6=dual/16bitRZ, 7=(reserved)]

PWMCON.3 PWM clock divide bits

PWMCON.2 PWM counter = clock / [1,4,16,64]

PWMCON.1 PWM clock source bits [1=F

XTAL

/15, 2=F

XTAL

PWMCON.0 3=T0 ext.int.rate, 4=F

VCO

(16.777MHz)]

PWM0H

PWM0L

PWM0 data registers

PWM1H

PWM1L

PWM1 data registers

DPCON

Data Pointer Control register

DPCON.6

data pointer auto-toggle enable (0=disable)

DPCON.5

shadow data pointer mode control bits

DPCON.4

[1=8052, 2=post-inc, 3=post-dec, 4=LSBtgl]

DPCON.3

main data pointer mode control bits

DPCON.2

[1=8052, 2=post-inc, 3=post-dec, 4=LSBtgl]

DPCON.1

(not implemented to allow INC DPCON toggling)

DPCON.0

data pointer select [0=main, 1=shadow]

T3CON

Timer 3 Control register

T3CON.7

Timer 3 baud rate enable (0=disable)

T3CON.2

binary divide factor (DIV)

T3CON.1

DIV = log[F

CORE

/(32·baudrate)] / log2

T3CON.0

(rounded down)

T3FD

Timer 3 Fractional Divider register

T3FD = (2·F

CORE

) / (baudrate·2

DIV

) - 64

MDO

master mode SDATA output bit

MDE

master mode SDATA output enable (0=disable)

MCO

master mode SCLK output bit

MDI

master mode SDATA input bit

I2CM

master mode select bit (0=slave mode)

I2CRS

serial port reset

I2CTX

transmission direction status (0=RX,1=TX)

I2CI

serial interface interrupt

I2CCON

I2C Control register

I2CADD

I2C Address register

I2CDAT

I2C Data register

lower RAM

details

SFRs

(direct

addressing

only)

128 bytes

upper RAM

(indirect

addressing

only)

128 bytes

lower RAM

(direct or

indirect

addressing)

00h

FFh

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