MSI A75MA-G55 - Manual (Page 48)

3-12
BIOS Setup MS-7696
Chapter 3
BIOS Setup MS-7696
Chapter 3
Advanced DRAM Configuraton
Press <Enter> to enter the sub-menu.
Command Rate
Ths settng controls the DRAM command rate.
tCL
Ths controls the CAS latency, whch determnes the tmng delay (n clock cycles)
before SDRAM starts a read command after recevng t.
tRCD
When DRAM s refreshed, both rows and columns are addressed separately. Ths
setup tem allows you to determne the tmng of the transton from RAS (row address
strobe) to CAS (column address strobe). The less the clock cycles, the faster the
DRAM performance.
tRP
Ths settng controls the number of cycles for Row Address Strobe (RAS) to be
allowed to precharge. If nsufficent tme s allowed for the RAS to accumulate ts
charge before DRAM refresh, refreshng may be ncomplete and DRAM may fal
to retan data. Ths tem apples only when synchronous DRAM s nstalled n the
system.
tRAS
Ths settng determnes the tme RAS takes to read from and wrte to memory cell.
tRC
The row cycle tme determnes the mnmum number of clock cycles a memory row
takes to complete a full cycle, from row actvaton up to the prechargng of the actve
row.
tWR
Mnmum tme nterval between end of wrte data burst and the start of a precharge
command. Allows sense amplfiers to restore data to cells.
tRRD
Specfies the actve-to-actve delay of dfferent banks.
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