Cypress CY7C1316CV18 - Manual (Page 3)

CY7C1316CV18, CY7C1916CV18
CY7C1318CV18, CY7C1320CV18
Document Number: 001-07160 Rev. *E Page 3 of 29
Logic Block Diagram (CY7C1318CV18)
Logic Block Diagram (CY7C1320CV18)
Write
Reg Write
Reg
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add
. Decode
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
18
36
18
BWS
[1:0]
V
REF
W
rite Add. Decode
18
20
C
C
18
LD
Control
Burst
Logic
A0
A
(19:1)
R/W
DOFF
5
12K x 18 A
rray
512K x 1
8
Array
19
18
DQ
[17:0]
18
CQ
CQ
Write
Reg Write
Reg
CLK
A
(18:0)
Gen.
K
K
Control
Logic
Address
Register
Read
A
d
d. Decode
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
36
72
36
BWS
[3:0]
V
REF
W
rite Add. Decode
36
19
C
C
36
LD
Control
Burst
Logic
A0
A
(18:1)
R/W
DOFF
256K x 36
Array
256K x
36 Array
18
36
DQ
[35:0]
36
CQ
CQ
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