Cypress CY7C1165V18 - Manual (Page 3)

CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Document Number: 001-06582 Rev. *D Page 3 of 29
Logic Block Diagram (CY7C1163V18)
Logic Block Diagram (CY7C1165V18)
256
K x 1
8
Array
CLK
A
(17:0)
Gen.
K
K
Control
Logic
Address
Register
D
[17:0]
Read Add. De
code
Read Data Reg.
RPS
WPS
Q
[17:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
18
18
72
18
BWS
[1:0]
V
REF
W
rite Add. De
code
Write
Reg
36
A
(17:0)
18
256
K x 1
8
Array
256
K x 1
8
Array
256
K x 1
8
Array
Write
Reg
Write
Reg
Write
Reg
18
CQ
CQ
DOFF
QVLD
128
K x 36 Array
CLK
A
(16:0)
Gen.
K
K
Control
Logic
Address
Register
D
[35:0]
R
ead Add. Decode
Read Data Reg.
RPS
WPS
Q
[35:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
72
17
36
144
36
BWS
[3:0]
V
REF
W
rite Add. Decode
Write
Reg
72
A
(16:0)
17
128
K x 36 Array
128
K x 36 Array
128
K x 36 Array
Write
Reg
Write
Reg
Write
Reg
36
CQ
CQ
DOFF
QVLD
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