Achronix Speedster22i Interlaken - Manual (Page 5)

Table of Figures
Figure 1: Shows a block diagram of IIPC with SerDes and user logic interface ............... 8
Figure 2: IIPC Hierarchy .................................................................................................... 9
Figure 3: RX Clock Domains ............................................................................................ 13
Figure 4: TX Clock Domains............................................................................................. 14
Figure 5: Sample TX Waveform with a 512-bit Data Bus ................................................. 25
Figure 6: Sample RX Waveform with a 512-bit Data Bus ................................................ 28
UG032, May 15, 2014 5