Achronix Speedster22i Memory PHY - Manual (Page 15)

UG043, April 26, 2014 15
Transmit path: If half-rate (or quarter-rate with the widebus wrapper) is used in the fabric,
four-wide data is provided from the fabric to a tx_sd module. The tx_sd module converts the
incoming data from half-rate to full-rate and provides a two-wide data into the tx_any
module (tx_sd module should be bypassed if a full-rate interface is used in the fabric). The
data passes from the tx_any module into the tx_flop module, which samples the transmit
data at both the positive and negative edges of the full-rate clock and aligns the data to the
dqs clock domain. This data is then passed to the transmit buffer before being sent out on the
pad.
Output Enable path: Full-rate output enables are passed from the fabric to the oeren_ny
module which passes the data to the oeren_flop. Similar to the tx_flop implementation,
oeren_flop samples the oe data at both the positive and negative edges of the full-rate clock
and aligns the data to the dqs clock domain. This is then fed as an output enable signal to the
transmit buffer. In addition, there is a termination resistance enable signal, opbit_rtt, that
goes through essentially the same path as the oe data, to turn on/off the input buffer
impedance when reading vs writing data.