Document Outline

• 1 User Information 6
• 2 Introduction 8
• 3 Specifications 11
• 4 Connectors 50
• 5 SMARC sAT30 Special Features 67
• 6 Thermal Design Considerations 76
• 7 SMARC sAT30 Software 78
• 8 SMARC sAT30 Boot Brief 79
• 9 SMARC sAT30 Programming Methods 82
• 10 Appendix A: Major Components BOM 83
• Figure 1: SMARC sAT30 Block Diagram 11
• 1.2 Copyright Notice
• 1.3 Trademarks
• 1.4 Quality Standards
• 1.5 Warranty
• 1.6 Technical Support
• 2 Introduction
  • 2.1 Feature Set Overview
  • 2.2 Software Support / Hardware Abstraction
  • 2.3 Document and Standards References
    • 2.3.1 External Industry Standard Documents
    • 2.3.2 Kontron Documents
    • 2.3.3 Kontron Schematics
    • 2.3.4 NVIDIA Hardware Documents
    • 2.3.5 NVIDIA Software Documents
    • 2.3.6 Kontron Software BSP
• 3 Specifications
  • 3.1 Functional Block Diagram
    • Figure 1: SMARC sAT30 Block Diagram
    • 3.2.2 Form Factor
    • 3.2.3 CPU
    • 3.2.4 Module Memory
    • 3.2.5 On-board Storage
    • 3.2.6 Clocks
    • 3.2.7 LVDS Serialized LCD Display Interface
      • Figure 2: T30 Module LVDS LCD Implementation
    • 3.2.8 Parallel LCD Display Interface
      • Figure 3: T30 Module Parallel LCD Implementation
    • 3.2.9 Carrier Based 24 bit Color Depth LVDS
    • 3.2.10 High-Definition-Multimedia-Interface (HDMI) Interface
    • 3.2.11 Camera Serial Interfaces (CSI) Interface
    • 3.2.12 USB Interfaces
      • Figure 4: External USB Port Power Distribution Logic Implementation
      • Figure 5: USB Power Distribution Implementation on Carrier
    • 3.2.13 PCIe Interfaces
    • 3.2.14 SATA Interface
    • 3.2.15 Gigabit Ethernet Controller (GbE) Interface
      • Figure 6 GbE Controller Implementation
    • 3.2.16 SDIO Interface
    • 3.2.17 SDMMC Interface for Carrier eMMC
    • 3.2.18 SPI Interfaces
    • 3.2.19 I2S Interfaces
    • 3.2.20 SPDIF Interface
    • 3.2.21 Asynchronous Serial Ports
    • 3.2.22 I2C Interface
  • 3.3 SMARC sAT30 Debug
    • 3.3.1 Serial Port for Linux Debug
    • 3.3.2 T30 CPU JTAG
  • 3.4 Mechanical Specifications
    • 3.4.1 Module Dimensions
    • 3.4.2 Height on Top
    • 3.4.3 Height on Bottom
    • 3.4.4 Layout Diagrams
      • Figure 7: SMARC sAT30 Top Side Components
      • Figure 9: SMARC sAT30 Bottom Side Components
    • 3.4.6 Module Cooling Solution Attachment
  • 3.5 Electrical Specification
    • 3.5.1 Supply Voltage
    • 3.5.2 RTC/Backup Voltage
    • 3.5.3 No Separate Standby Voltage
    • 3.5.4 Module I/O Voltage
    • 3.5.5 Power Consumption
  • 3.6 Environmental Specification
    • 3.6.1 Operating Temperature
    • 3.6.2 Humidity
    • 3.6.3 RoHS Compliance
• 4 Connectors
  • 4.1 SMARC sAT30 Edge Connector Pin Mapping
    • Figure 11: SMARC sAT30 edge finger primary pins
  • 4.2 JTAG
    • Figure 13: SMARC sAT30 JTAG Connectors
    • Figure 14: T30 CPU JTAG
    • Figure 15: CPLD JTAG
• 5 SMARC sAT30 Special Features
  • 5.1 Watchdog Timer
    • 5.1.1 CPLD Watchdog Timer
    • 5.1.2 Tegra T30 SoC Watchdog Timer
  • 5.2 PMU GPIO
  • 5.3 SMARC sAT30 I/O
  • 5.4 Temperature Sensor
  • 5.5 SMARC sAT30 Power Management
  • 5.6 Board ID EEPROM
• 6 Thermal Design Considerations
  • 6.1 Thermal Management
  • 6.2 Heat Spreader Dimensions
    • Figure 16: Heat Spreader
  • 6.3 Thermal Parameters
  • 6.4 Operation without a Heat Spreader / Heat Sink
• 7 SMARC sAT30 Software
  • 7.1 Introduction
  • 7.2 Linux for Tegra
  • 7.3 SMARC sAT30 Linux for Tegra Modifications
  • 7.4 Kontron BSP (Board Support Package)
• 8 SMARC sAT30 Boot Brief
  • 8.1 SMARC sAT30 Boot Up Sequence
  • 8.2 BOOT Selection
    • Figure 17: Boot Selection Strap Implementation
• 9 SMARC sAT30 Programming Methods
  • 9.1 eMMC Flash & External SD Card Programming Using Force Recovery Method
  • 9.2 SPI Flash Programming
• 10 Appendix A: Major Components BOM
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