Cypress CY7C1318CV18-200BZI - Manual (Page 17)

CY7C1318CV18
CY7C1320CV18
Document Number: 001-07160 Rev. *F Page 17 of 26
Power Up Sequence in DDR II SRAM
DDR II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power Up Sequence
■ Apply power and drive DOFF either HIGH or LOW (all other
inputs can be HIGH or LOW).
❐ Apply V
DD
before V
DDQ
.
❐ Apply V
DDQ
before V
REF
or at the same time as V
REF
.
❐ Drive DOFF HIGH.
■ Provide stable DOFF (HIGH), power, and clock (K, K) for 1024
cycles to lock the DLL.
DLL Constraints
■ DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as t
KC Var
.
■ The DLL functions at frequencies down to 120 MHz.
■ If the input clock is unstable and the DLL is enabled, then the
DLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide1024 cycles stable clock
to relock to the desired clock frequency.
Figure 3. Power Up Waveforms
> 1024 Stable clock Start Normal
Operation
DOFF
Stable (< +/- 0.1V DC per 50ns )
Fix High (or tie to VDDQ)
K
K
DDQ DD
V V /
DDQ DD V V /
Clock Start (Clock Starts after Stable)
DDQ DD V V /
~ ~
~~
Unstable Clock
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