Logic block diagram (cy7c1143v18), Logic block diagram (cy7c1145v18) – Cypress CY7C1143V18 User Manual
Page 3
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CY7C1141V18, CY7C1156V18
CY7C1143V18, CY7C1145V18
Document Number: 001-06583 Rev. *D
Page 3 of 28
Logic Block Diagram (CY7C1143V18)
Logic Block Diagram (CY7C1145V18)
256K
x 1
8
Arra
y
CLK
A
(17:0)
Gen.
K
K
Control
Logic
Address
Register
D
[17:0]
R
ead Add.
D
e
code
Read Data Reg.
RPS
WPS
Q
[17:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
18
18
72
18
BWS
[1:0]
V
REF
W
rite Add.
D
e
code
Write
Reg
36
A
(17:0)
18
256K
x 1
8
Arra
y
256K
x 1
8
Arra
y
256K
x 1
8
Arra
y
Write
Reg
Write
Reg
Write
Reg
18
CQ
CQ
DOFF
QVLD
128K
x 3
6
Arra
y
CLK
A
(16:0)
Gen.
K
K
Control
Logic
Address
Register
D
[35:0]
R
ead Add.
D
e
code
Read Data Reg.
RPS
WPS
Q
[35:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
72
17
36
144
36
BWS
[3:0]
V
REF
W
rite Add.
D
e
code
Write
Reg
72
A
(16:0)
17
128K
x 3
6
Arra
y
128K
x 3
6
Arra
y
128K
x 3
6
Arra
y
Write
Reg
Write
Reg
Write
Reg
36
CQ
CQ
DOFF
QVLD
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