Toshiba FS-160 SERIES User Manual
Page 41
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+5VSW
The +5VSW circuit receives the
ACLO signal as an input as
shown in Fig, 5.8, VJhen ACLO
goes high, it outputs 5V.
The output is connected to the
pull-up resistor for each out
put port of the CPU and PRC.
The reason why this circuit is
required is described below.
When ACLO is at the low level
(the CPU and PRC are reset),
the output ports of the CPU and
PRC become unstable. So this
circuit stops application of
+5V while the CPU and PRC are
reset, to prevent malfunction
of the ROM, RAM and printer
due to transmission of unneces
sary signals.
The timing and voltage values of the above outputs are shown in
Fig, 5,9 and Table 5,1, respectively.
Fig. 5.8
+5VSW Circuit
AC IN
Pig, 5,9 PS Timing Chart
tl i Sms
t2 ^ 0ms
t3 £ 40ms
t4 *
—— 2.
2
t3 "
{t4=400ms=TYP)
-24-