Maxim Integrated DS80C390 - Manual (Page 15)

DS80C390
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The reset default of one Stretch cycle results in a three cycle MOVX for any external access. Therefore,
the default off-chip RAM access is not at full speed. This is a convenience to existing designs that utilize
slower RAM. When maximum speed is desired, software should select a Stretch value of zero. When
using very slow RAM or peripherals, the application software can select a larger Stretch value.
The specific timing of MOVX instructions as a function of Stretch settings is provided in the Electrical
Specifications section of this data sheet. As an example, Table 8 shows the read and write strobe widths
corresponding to each Stretch value.
DATA MEMORY CYCLE STRETCH VALUES Table 8
RD , WR Pulse Width (in oscillator clocks) MD2 MD1 MD0 Stretch
Cycle
Count
MOVX
Machine
Cycles
t
MCS
(4X/ 2X = 1
CD1:0 = 00)
t
MCS
(4X/ 2X = 0
CD1:0 = 00)
t
MCS
(4X/ 2X = X
CD1:0 = 10)
t
MCS
(4X/ 2X = X
CD1:0 = 11)
0 0 0 0* 2 0.5 t
CLCL
1 t
CLCL
2 t
CLCL
2048 t
CLCL
0 0 1 1** 3 t
CLCL
2 t
CLCL
4 t
CLCL
4096 t
CLCL
0 1 0 2 4 2 t
CLCL
4 t
CLCL
8 t
CLCL
8192 t
CLCL
0 1 1 3 5 3 t
CLCL
6 t
CLCL
12 t
CLCL
12288 t
CLCL
1 0 0 4 9 4 t
CLCL
8 t
CLCL
16 t
CLCL
16384 t
CLCL
1 0 1 5 10 5 t
CLCL
10 t
CLCL
20 t
CLCL
20480 t
CLCL
1 1 0 6 11 6 t
CLCL
12 t
CLCL
24 t
CLCL
24576 t
CLCL
1 1 1 7 12 7 t
CLCL
14 t
CLCL
28 t
CLCL
28672 t
CLCL
*All internal MOVX operations execute at the 0 Stretch setting.
** Default Stretch setting for external MOVX operations following reset.
EXTENDED STACK POINTER
The DS80C390 supports both the traditional 8-bit and an extended 10-bit stack pointer that improves the
performance of large programs written in high-level languages such as C. The 10-bit stack pointer
feature is enabled by setting the Stack Address Mode bit, SA (ACON.2). The bit is cleared following a
reset, forcing the device to use an 8-bit stack located in the Scratchpad RAM area. When the SA bit is
set, the device will address up to 1kB of stack memory in the first 1kB of the internal MOVX memory.
The 10-bit stack pointer address is generated by concatenating the lower two bits of the Extended Stack
Pointer (ESP;9Bh) and the traditional 8051 Stack Pointer (SP;81h). The 10-bit stack pointer cannot be
enabled when the 4kB of SRAM is mapped as both program and data memory.