Document Outline

• TABLE OF CONTENTS
• SECTION 1: Overview
• SECTION 2: Architecture
  • 2.1 Instruction Decoding
  • 2.2 Register Space
  • 2.3 Memory Organization
    • 2.3.1 Program Memory
    • 2.3.2 Utility ROM
    • 2.3.3 Data Memory
    • 2.3.4 Stack Memory
  • 2.4 Memory Management Unit
  • 2.5 Memory Mapping
    • 2.5.1 Memory Mapping Into Data Space
    • 2.5.2 Memory Mapping into Code Space
    • 2.5.3 Memory Mapping Rules
  • 2.6 Memory Protection
    • 2.6.1 Rules for System Software
    • 2.6.2 Privilege Exception Interrupt
    • 2.6.3 Memory Access Protection Impact on Data Pointers (and Code Pointer)
    • 2.6.4 Debugging
    • 2.6.5 Enabling Memory Protection
    • 2.6.6 Reset Procedure and Setup of Memory Protection
    • 2.6.7 Loader Access Control
    • 2.6.8 Disabling MAXQ610-Specific Memory Access Features
    • 2.6.9 No User-Loader Segment
  • 2.7 Clock Generation
    • 2.7.1 External Clock (Crystal/Resonator)
    • 2.7.2 External Clock (Direct Input)
    • 2.7.3 Internal System Clock Generation
  • 2.8 Wake-Up Timer
    • 2.8.1 Using the Wake-Up Timer to Exit Stop Mode
  • 2.9 Interrupts
    • 2.9.1 Servicing Interrupts
    • 2.9.2 Interrupt System Operation
    • 2.9.3 Synchronous vs. Asynchronous Interrupt Sources
    • 2.9.4 Interrupt Prioritization by Software
    • 2.9.5 Interrupt Exception Window
  • 2.10 Operating Modes
  • 2.11 Reset Mode
    • 2.11.1 Power-On/Power-Fail Reset
    • 2.11.2 External Reset
    • 2.11.3 Watchdog Timer Reset
    • 2.11.4 Internal System Reset
  • 2.12 Power-Management Mode
    • 2.12.1 Switchback
  • 2.13 Stop Mode
• SECTION 3: Programming
  • 3.1 Addressing Modes
  • 3.2 Prefix Operations
  • 3.3 Reading and Writing Registers
    • 3.3.1 Loading an 8-Bit Register with an Immediate Value
    • 3.3.2 Loading a 16-Bit Register with a 16-Bit Immediate Value
    • 3.3.3 Moving Values Between Registers of the Same Size
    • 3.3.4 Moving Values Between Registers of Different Sizes
    • 3.3.5 8-Bit Destination ← Low Byte (16-Bit Source)
    • 3.3.6 8-Bit Destination ← High Byte (16-Bit Source)
    • 3.3.7 16-Bit Destination ← Concatenation (8-Bit Source, 8-Bit Source)
    • 3.3.8 Low (16-Bit Destination) ← 8-Bit Source
    • 3.3.9 High (16-Bit Destination) ← 8-Bit Source
  • 3.4 Reading and Writing Register Bits
  • 3.5 Using the Arithmetic and Logic Unit
    • 3.5.1 Selecting the Active Accumulator
    • 3.5.2 Enabling Autoincrement and Autodecrement
    • 3.5.3 ALU Operations Using the Active Accumulator and a Source
    • 3.5.4 ALU Operations Using Only the Active Accumulator
    • 3.5.5 ALU Bit Operations Using Only the Active Accumulator
    • 3.5.6 Example: Adding Two 4-Byte Numbers Using Autoincrement
  • 3.6 Processor Status Flag Operations
    • 3.6.1 Sign Flag
    • 3.6.2 Zero Flag
    • 3.6.3 Equals Flag
    • 3.6.4 Carry Flag
    • 3.6.5 Overflow Flag
  • 3.7 Controlling Program Flow
    • 3.7.1 Obtaining the Next Execution Address
    • 3.7.2 Unconditional jumps
    • 3.7.3 Conditional Jumps
    • 3.7.4 Calling Subroutines
    • 3.7.5 Loop Operations
    • 3.7.6 Conditional Returns
    • 3.7.7 Conditional Return from Interrupt
  • 3.8 Accessing the Stack
  • 3.9 Accessing Data Memory
  • 3.10 Using the Watchdog Timer
• SECTION 4: System Register Description
  • 4.1 System Register Descriptions
• SECTION 5: Peripheral Register Modules
  • 5.1 Peripheral Register Bit Descriptions
• SECTION 6: General-Purpose I/O Module
  • 6.1 Port Pin Register Descriptions
    • 6.1.1 Port Pin Example 1: Driving Outputs on Port 0
    • 6.1.2 Port Pin Example 2: Receiving Inputs on Port 1
  • 6.2 External Interrupt Register Descriptions
• SECTION 7: Timer/Counter Type B
  • 7.1 Timer B
    • 7.1.1 Timer B Mode: Autoreload Mode
    • 7.1.2 Timer B Mode: Capture Mode
    • 7.1.3 Timer B Mode: Up/Down Autoreload Mode
    • 7.1.4 Timer B Mode: Clock Output Mode
    • 7.1.5 Timer B Mode: PWM Output Function
      • 7.1.5.1 Timer B Mode: Up-Counting PWM Output Mode
      • 7.1.5.2 Timer B Mode: Up/Down-Count PWM Output Mode
    • 7.1.6 Timer B Input Clock
  • 7.2 Timer/Counter B Peripheral Registers
    • 7.2.1 Timer B Control Register (TBCN)
    • 7.2.2 Timer B Value Register (TBV)
    • 7.2.3 Timer B Capture/Reload Value Register (TBR)
    • 7.2.4 Timer B Compare Register (TBC)
• SECTION 8: IR Timer
  • 8.1 Carrier Generation Module
  • 8.2 IR Transmission
  • 8.3 IR Transmit—Independent External Carrier and Modulator Outputs
  • 8.4 IR Receive
  • 8.5 Carrier Burst-Count Mode
  • 8.6 IRV Stand-Alone Count Mode
  • 8.7 IR Timer Peripheral Registers
    • 8.7.1 IR Control Register (IRCN)
    • 8.7.2 IR Control Register B (IRCNB)
    • 8.7.3 IR Value Register (IRV)
    • 8.7.4 IR Carrier Register (IRCA)
    • 8.7.5 IR Modulator Time Register (IRMT)
• SECTION 9: Serial I/O Module
  • 9.1 USART Modes
    • 9.1.1 USART Mode 0
    • 9.1.2 USART Mode 1
    • 9.1.3 USART Mode 2
    • 9.1.4 USART Mode 3
  • 9.2 Baud-Rate Generation
    • 9.2.1 Mode 0 Baud Rate
    • 9.2.2 Mode 2 Baud Rate
    • 9.2.3 Mode 1 or 3 Baud Rate
    • 9.2.4 Baud-Clock Generator
  • 9.3 Framing Error Detection
  • 9.4 USART Peripheral Registers
    • 9.4.1 Serial Control Register (SCON)
    • 9.4.2 Serial Port Mode Register (SMD)
    • 9.4.3 Serial Port Data Buffer Register (SBUF)
    • 9.4.4 Serial Port Phase Register (PR)
• SECTION 10: Serial Peripheral Interface (SPI) Module
  • 10.1 SPI Transfer Formats
  • 10.2 SPI Slave Select
  • 10.3 SPI Character Lengths
  • 10.4 SPI Transfer Baud Rates
  • 10.5 SPI System Errors
    • 10.5.1 Mode Fault
    • 10.5.2 Receive Overrun
    • 10.5.3 Write Collision While Busy
  • 10.6 SPI Master Operation
  • 10.7 SPI Slave Operation
  • 10.8 SPI Peripheral Registers
    • 10.8.1 SPI Control Register (SPICN)
    • 10.8.2 SPI Configuration Register (SPICF)
    • 10.8.3 SPI Clock Register (SPICK)
    • 10.8.4 SPI Data Buffer Register (SPIB)
• SECTION 11: Test Access Port (TAP)
  • 11.1 TAP Controller
  • 11.2 TAP State Control
    • 11.2.1 Test-Logic-Reset
    • 11.2.2 Run-Test-Idle
    • 11.2.3 IR-Scan Sequence
    • 11.2.4 DR-Scan Sequence
  • 11.3 Communication Through TAP
    • 11.3.1 TAP Communication Examples—IR-Scan and DR-Scan
• SECTION 12: In-Circuit Debug Mode
  • 12.1 Background Mode Operation
  • 12.2 Breakpoint Registers
    • 12.2.1 Breakpoint n Register (BPn, n = 0 to 3)
    • 12.2.2 Breakpoint 4 Register (BP4)
    • 12.2.3 Breakpoint 5 Register (BP5)
    • 12.2.4 Using Breakpoints
  • 12.3 Debug Mode
    • 12.3.1 Debug Mode Commands
    • 12.3.2 Read Register Map Command Host-Utility ROM Interaction
    • 12.3.3 Single-Step Operation (Trace)
    • 12.3.4 Return
    • 12.3.5 Debug Mode Special Considerations
  • 12.4 In-Circuit Debug Peripheral Registers
    • 12.4.1 In Circuit Debug Temp 0/1 Register (ICDT0/ICDT1)
    • 12.4.2 In-Circuit Debug Control Register (ICDC)
    • 12.4.3 In-Circuit Debug Flag Register (ICDF)
    • 12.4.4 In-Circuit Debug Buffer Register (ICDB)
    • 12.4.5 In-Circuit Debug Data Register (ICDD)
    • 12.4.6 In-Circuit Debug Address Register (ICDA)
• SECTION 13: In-System Programming (JTAG)
  • 13.1 JTAG Bootloader Operation
  • 13.2 Password-Protected Access
    • 13.2.1 Entering Passwords
• SECTION 14: MAXQ610 Instruction Set Summary
• SECTION 15: Utility ROM
  • 15.1 In-Application Programming Functions
    • 15.1.1 UROM_flashWrite
    • 15.1.2 UROM_flashErasePage
    • 15.1.3 UROM_flashEraseAll
  • 15.2 Data Transfer Functions
    • 15.2.1 UROM_moveDP0
    • 15.2.2 UROM_moveDP0inc
    • 15.2.3 UROM_moveDP0dec
    • 15.2.4 UROM_moveDP1
    • 15.2.5 UROM_moveDP1inc
    • 15.2.6 UROM_moveDP1dec
    • 15.2.7 UROM_moveFP
    • 15.2.8 UROM_moveFPinc
    • 15.2.9 UROM_moveFPdec
    • 15.2.10 UROM_moveBP
    • 15.2.11 UROM_copyBuffer
  • 15.3 Miscellaneous Functions
    • 15.3.1 UROM_stopMode
  • 15.4 ROM Example 1: Calling A Utility ROM Function Directly
  • 15.5 ROM Example 2: Calling A Utility ROM Function Indirectly
• REVISION HISTORY