Document Outline

• ADDENDUM TO SECTION 1: OVERVIEW
  • 1.1 References
• ADDENDUM TO SECTION 2: ARCHITECTURE
  • 2.1 Instruction Set
  • 2.2 Harvard Memory Architecture
  • 2.3 Register Space
  • 2.4 Memory Organization
    • 2.4.1 Register Space
    • 2.4.2 Program Stack
    • 2.4.3 Data SRAM
    • 2.4.4 Program Flash
  • 2.5 Program and Data Memory Mapping
  • 2.6 Clock Generation
    • 2.6.1 External High-Frequency Oscillator Circuit
    • 2.6.2 Ring Oscillator
  • 2.7 Interrupts
  • 2.8 Reset Conditions
    • 2.8.1 Power-On Reset
    • 2.8.2 Watchdog Timer Reset
    • 2.8.3 External Reset
  • 2.9 Power-Management Features
    • 2.9.1 Divide-by-256 Mode (PMM)
    • 2.9.2 Switchback Mode
    • 2.9.3 Stop Mode
• ADDENDUM TO SECTION 3: PROGRAMMING
• ADDENDUM TO SECTION 4: SYSTEM REGISTER DESCRIPTIONS
  • 4.1 System Register Descriptions
    • 4.1.1 Processor Status Flags Register (PSF, M8[04h])
    • 4.1.2 Interrupt Mask Register (IMR, M8[06h])
    • 4.1.3 System Control Register (SC, M8[08h])
    • 4.1.4 Interrupt Identification Register (IIR, M8[0Bh])
    • 4.1.5 System Clock Control Register (CKCN, M8[0Eh])
• ADDENDUM TO SECTION 5: PERIPHERAL REGISTER MODULES
• ADDENDUM TO SECTION 6: GENERAL-PURPOSE I/O MODULE
  • 6.1 GPIO and External Interrupt Register Descriptions
    • 6.1.1 Port 0 Direction Register (PD0, M0[10h])
    • 6.1.2 Port 1 Direction Register (PD1, M0[11h])
    • 6.1.3 Port 0 Input Disable Register (PID0, M0[0Dh])
    • 6.1.4 Port 0 Output Register (PO0, M0[00h])
    • 6.1.5 Port 1 Output Register (PO1, M0[01h])
    • 6.1.6 Port 0 Input Register (PI0, M0[08h])
    • 6.1.7 Port 1 Input Register (PI1, M0[09h])
    • 6.1.8 External Interrupt Flag 0 Register (EIF0, M0[02h])
    • 6.1.9 External Interrupt Flag 1 Register (EIF1, M0[04h])
    • 6.1.10 External Interrupt Enable 0 Register (EIE0, M0[03h])
    • 6.1.11 External Interrupt Enable 1 Register (EIE1, M0[05h])
    • 6.1.12 External Interrupt Edge Select 0 Register (EIES0, M0[0Ah])
    • 6.1.13 External Interrupt Edge Select 1 Register (EIES1, M0[0Bh])
  • 6.2 Port Pin Examples
    • 6.2.1 Port Pin Example 1: Driving Outputs on Port 0
    • 6.2.2 Port Pin Example 2: Receiving Inputs on Port 0
• ADDENDUM TO SECTION 7: TIMER/COUNTER 0 MODULE
• ADDENDUM TO SECTION 8: TIMER/COUNTER 1 MODULE
• ADDENDUM TO SECTION 9: TIMER/COUNTER 2 MODULE
• ADDENDUM TO SECTION 10: SERIAL I/O MODULE
  • 10.1 Serial USART I/O Pins and Control Registers
  • 10.2 Serial USART Code Examples
    • 10.2.1 Serial USART Example: Echo Characters in 10-Bit Asynchronous Mode
• ADDENDUM TO SECTION 11: SERIAL PERIPHERAL INTERFACE (SPI) MODULE
  • 11.1 SPI Input/Output Pins and Control Registers
  • 11.2 SPI Code Examples
    • 11.2.1 SPI Example 1: Transmitting Data in Master Mode
    • 11.2.2 SPI Example 2: Receiving Data in Slave Mode
• ADDENDUM TO SECTION 12: HARDWARE MULTIPLIER MODULE
  • 12.1 Hardware Multiplier Control Registers
  • 12.2 Hardware Multiplier Code Examples
    • 12.2.1 Hardware Multiplier Example: Multiply and Square/Accumulate
• ADDENDUM TO SECTION 13: 1-Wire BUS MASTER
• ADDENDUM TO SECTION 14: REAL-TIME CLOCK MODULE
• ADDENDUM TO SECTION 15: TEST ACCESS PORT (TAP)
• ADDENDUM TO SECTION 16: IN-CIRCUIT DEBUG MODE
  • 16.1 Register Read and Write Commands
  • 16.2 Data Memory Read Command
  • 16.3 Data Memory Write Command
  • 16.4 Program Stack Read Command
  • 16.5 Read Register Map Command
• ADDENDUM TO SECTION 17: IN-SYSTEM PROGRAMMING (JTAG)
  • 17.1 JTAG Bootloader Protocol
  • 17.2 Family 0 Commands (Not Password Protected)
  • 17.3 Family 1 Commands: Load Variable Length (Password Protected)
  • 17.4 Family 2 Commands: Dump Variable Length (Password Protected)
  • 17.5 Family 3 Commands: CRC Variable Length (Password Protected)
  • 17.6 Family 4 Commands: Verify Variable Length (Password Protected)
  • 17.7 Family 5 Commands: Load and Verify Variable Length (Password Protected)
  • 17.8 Family E Commands: Erase Fixed Length (Password Protected)
• ADDENDUM TO SECTION 18: MAXQ FAMILY INSTRUCTION SET SUMMARY
• SECTION 19: ANALOG-TO-DIGITAL CONVERTER (SPECIFIC TO MAXQ8913)
  • 19.1 Analog-to-Digital Converter Features
  • 19.2 Analog-to-Digital Pins and Control Registers
    • 19.2.1 Analog-to-Digital Converter Status Register (ADST, M4[06h])
    • 19.2.2 ADC Conversion Sequence Address Register (ADADDR, M3[01h])
    • 19.2.3 ADC Control Register (ADCN, M3[08h])
    • 19.2.4 ADC Data Register (ADDATA, M3[09h])
    • 19.2.5 ADC Data Buffer Registers (ADBUF[0] to ADBUF[15], ADDATA[00h] to ADDATA[0Fh])
    • 19.2.6 ADC Conversion Configuration Registers (ADCFG[0] to ADCFG[7], ADDATA[10h] to ADDATA[17h])
    • 19.2.7 Temperature Sensor Enable Register (TEMPEN, M3[0Ch])
  • 19.3 Analog-to-Digital Converter Code Examples
    • 19.3.1 ADC Example 1: Single Conversion
    • 19.3.2 ADC Example 2: Continuous Conversion
• SECTION 20: DIGITAL-TO-ANALOG CONVERTERS (SPECIFIC TO MAXQ8913)
  • 20.1 DAC Overview
  • 20.2 DAC Control Register Descriptions
    • 20.2.1 DAC 1 Output Register (DAC1OUT, M3[02h])
    • 20.2.2 DAC 2 Output Register (DAC2OUT, M3[03h])
    • 20.2.3 DAC 3 Output Register (DAC3OUT, M3[04h])
    • 20.2.4 DAC 4 Output Register (DAC4OUT, M3[05h])
    • 20.2.5 Current Sink Control Register (ISINKCN, M3[07h])
• SECTION 21: TIMER/COUNTER B MODULE (SPECIFIC TO MAXQ8913)
  • 21.1 Timer/Counter B Register Descriptions
    • 21.1.1 Timer B Timer/Counter Capture/Reload Register (TBR, M2[07h])
    • 21.1.2 Timer B Timer/Counter Compare Register (TBC, M2[0Bh])
    • 21.1.3 Timer B Timer/Counter Control Register (TBCN, M2[06h])
    • 21.1.4 Timer B Timer Value Register (TBV, M2[0Ah])
  • 21.2 Timer/Counter B Operation
    • 21.2.1 Timer B 16-Bit Timer/Counter Mode with Autoreload
    • 21.2.2 Timer B 16-Bit Capture Mode
    • 21.2.3 Timer B 16-Bit Up/Down Count with Autoreload Mode
    • 21.2.4 Timer B Clock Output Mode
    • 21.2.5 Timer B PWM/Output Control Functionality
    • 21.2.6 16-Bit Up Count PWM/Output Control Mode
    • 21.2.7 16-Bit Up/Down Count PWM/Output Control Mode
    • 21.2.8 EXENB Control During PWM/Output Control Mode
  • 21.3 Timer B Examples
    • 21.3.1 Timer B Example: Reloading Timer Mode
• SECTION 22 : I2C BUS INTERFACE (SPECIFIC TO MAXQ8913)
  • 22.1 I2C Register Descriptions
    • 22.1.1 I2C Data Buffer Register (I2CBUF, M1[06h])
      • 22.1.1.1 I2C Data Read and Write
      • 22.1.1.2 I2C Address Transmission
    • 22.1.2 I2C Status Register (I2CST, M3[01h])
    • 22.1.3 I2C Interrupt Enable Register (I2CIE, M1[07h])
    • 22.1.4 I2C Control Register (I2CCN, M1[04h])
    • 22.1.5 I2C Clock Control Register (I2CCK, M1[0Ch])
    • 22.1.6 I2C Timeout Register (I2CTO, M1[0Dh])
    • 22.1.7 I2C Slave Address Register (I2CSLA, M1[0Eh])
  • 22.2 I2C Code Examples
    • 22.2.1 I2C Example 1: Master Mode Transmit
    • 22.2.2 I2C Example 2: Master Mode Receive
    • 22.2.3 I2C Example 3: Slave Mode Receive
    • 22.2.4 I2C Example 4: Slave Mode Receive
• SECTION 23: SUPPLY VOLTAGE MONITOR AND POWER CONTROL (SPECIFIC TO MAXQ8913)
  • 23.1 SVM and Power Control Register Descriptions
    • 23.1.1 Power Control Register (PWCN, M0[0Ch])
    • 23.1.2 Supply Voltage Monitor Register (SVM, M0[06h])
• SECTION 24: INPUT/OUTPUT AMPLIFIERS (SPECIFIC TO MAXQ8913)
  • 24.1 Input/Output Amplifier Overview
  • 24.2 Amplifier Control Register Descriptions
    • 24.2.1 Amplifier Control Register (AMPCN, M3[06h])
    • 24.2.2 Op Amp Control Register (OPMCN, M3[0Ah])
• SECTION 25: UTILITY ROM (SPECIFIC TO MAXQ8913)
  • 25.1 Overview
  • 25.2 In-Application Programming Functions
    • 25.2.1 UROM_flashWrite
    • 25.2.2 UROM_flashErasePage
    • 25.2.3 UROM_flashEraseAll
  • 25.3 Data Transfer Functions
    • 25.3.1 UROM_moveDP0
    • 25.3.2 UROM_moveDP0inc
    • 25.3.3 UROM_moveDP0dec
    • 25.3.4 UROM_moveDP1
    • 25.3.5 UROM_moveDP1inc
    • 25.3.6 UROM_moveDP1dec
    • 25.3.7 UROM_moveBP
    • 25.3.8 UROM_moveBPinc
    • 25.3.9 UROM_moveBPdec
    • 25.3.10 UROM_copyBuffer
  • 25.4 Utility ROM Examples
    • 25.4.1 Utility ROM Example 1: Reading Constant Word Data from Flash
    • 25.4.2 Utility ROM Example 2: Reading Constant Byte Data from Flash (Indirect Function Call)
• APPENDIX 1: MAXQ8913 DEVICE INCLUDE FILE FOR MAX-IDE
• REVISION HISTORY