Document Outline

• 1. INTRODUCTION
• 2. ORDERING INFORMATION
• 3. ARCHITECTURE
  • 3.1 ALU
  • 3.2 Special Function Registers (SFRs)
    • 3.2.1 Accumulator
    • 3.2.2 B Register
    • 3.2.3 Program Status Word
    • 3.2.4 Data Pointer(s)
    • 3.2.5 Stack Pointer
    • 3.2.6 I/O Ports
    • 3.2.7 Timer/Counters
    • 3.2.8 UARTs
    • 3.2.9 Scratchpad Registers (RAM)
    • 3.2.10 Stack
    • 3.2.11 Working Registers
    • 3.2.12 Program Counter
    • 3.2.13 Address/Data Bus
    • 3.2.14 Watchdog Timer
    • 3.2.15 Power Monitor
    • 3.2.16 Interrupts
    • 3.2.17 Timing Control
    • 3.2.18 Real-Time Clock
    • 3.2.19 Feature Summary
• 4. PROGRAMMING MODEL
  • 4.1 Memory Organization
    • 4.1.1 Memory Map
    • 4.1.2 Register Map
      • 4.1.2.1 Bit-Addressable Locations
      • 4.1.2.2 Working Registers
      • 4.1.2.3 Stack
  • 4.2 Special Function Registers
    • 4.2.1 Port 0 (P0)
    • 4.2.2 Stack Pointer (SP)
    • 4.2.3 Data Pointer Low 0 (DPL)
    • 4.2.4 Data Pointer High 0 (DPH)
    • 4.2.5 Data Pointer Low 1 (DPL1)
    • 4.2.6 Data Pointer High 1 (DPH1)
    • 4.2.7 Data Pointer Select (DPS)
    • 4.2.8 Power Control (PCON)
    • 4.2.9 Timer/Counter Control (TCON)
    • 4.2.10 Timer Mode Control (TMOD)
    • 4.2.11 Timer 0 LSB (TL0)
    • 4.2.12 Timer 1 LSB (TL1)
    • 4.2.13 Timer 0 MSB (TH0)
    • 4.2.14 Timer 1 MSB (TH1)
    • 4.2.15 Clock Control (CKCON)
    • 4.2.16 Port 1 (P1)
    • 4.2.17 External Interrupt Flag (EXIF)
    • 4.2.18 RTC Trim Register (TRIM)
    • 4.2.19 Serial Port 0 Control (SCON0)
    • 4.2.20 Serial Data Buffer 0 (SBUF0)
    • 4.2.21 Port 2 (P2)
    • 4.2.22 Interrupt Enable (IE)
    • 4.2.23 Slave Address Register 0 (SADDR0)
    • 4.2.24 Slave Address Register 1 (SADDR1)
    • 4.2.25 Port 3 (P3)
    • 4.2.26 Interrupt Priority (IP)
    • 4.2.27 Slave Address Mask Enable Register 0 (SADEN0)
    • 4.2.28 Slave Address Mask Enable Register 1 (SADEN1)
    • 4.2.29 Serial Port Control (SCON1)
    • 4.2.30 Serial Data Buffer 1 (SBUF1)
    • 4.2.31 ROM Size Select (ROMSIZE)
    • 4.2.32 Power Management Register (PMR)
      • 4.2.32.1 System Control Byte Description (EPROM; FFFCh)
    • 4.2.33 Status Register (STATUS)
    • 4.2.34 Timed Access Register (TA)
    • 4.2.35 Timer 2 Control (T2CON)
    • 4.2.36 Timer 2 Mode (T2MOD)
    • 4.2.37 Timer 2 Capture LSB (RCAP2L)
    • 4.2.38 Timer 2 Capture MSB (RCAP2H)
    • 4.2.39 Timer 2 LSB (TL2)
    • 4.2.40 Timer 2 MSB (TH2)
    • 4.2.41 Program Status Word (PSW)
    • 4.2.42 Watchdog Control (WDCON)
    • 4.2.43 Accumulator (A or ACC)
    • 4.2.44 Extended Interrupt Enable (EIE)
    • 4.2.45 B Register (B)
    • 4.2.46 Real-Time Alarm Subsecond Register (RTASS)
    • 4.2.47 Real-Time Alarm Second Register (RTAS)
    • 4.2.48 Real-Time Alarm Minute Register (RTAM)
    • 4.2.49 Real-Time Alarm Hour Register (RTAH)
    • 4.2.50 Extended Interrupt Priority (EIP)
    • 4.2.51 Real-Time Clock Control Register (RTCC)
    • 4.2.52 Real-Time Clock Subsecond Register (RTCSS)
    • 4.2.53 Real-Time Clock Second Register (RTCS)
    • 4.2.54 Real-Time Clock Minute Register (RTCM)
    • 4.2.55 Real-Time Clock Hour Register (RTCH)
    • 4.2.56 Real-Time Clock Day Register 0 (RTCD0)
    • 4.2.57 Real-Time Clock Day Register 1 (RTCD1)
  • 4.3 Instruction Timing
  • 4.4 Addressing Modes
    • 4.4.1 Register Addressing
    • 4.4.2 Direct Addressing
    • 4.4.3 Register Indirect Addressing
    • 4.4.4 Immediate Addressing
    • 4.4.5 Register Indirect with Displacement
    • 4.4.6 Relative Addressing
    • 4.4.7 Page Addressing
    • 4.4.8 Extended Addressing
  • 4.5 Program Status Flags
    • 4.5.1 Bit Descriptions
• 5. CPU TIMING
  • 5.1 Oscillator
  • 5.2 XTAL1
  • 5.3 XTAL2
  • 5.4 Oscillator Characteristics
  • 5.5 Crystal Selection
  • 5.6 Instruction Timing
    • 5.6.1 Single-Cycle Instructions
    • 5.6.2 Two-Cycle Instructions
    • 5.6.3 Three-Cycle Instructions
    • 5.6.4 Four-Cycle Instructions
    • 5.6.5 Five-Cycle Instructions
  • 5.7 Comparison to the 8051
• 6. MEMORY ACCESS
  • 6.1 Internal Program Memory
  • 6.2 Internal Data Memory
    • 6.2.1 ROMSIZE Feature
  • 6.3 Program Memory Interconnect
  • 6.4 Data Memory Interconnect
  • 6.5 Data Memory Access
    • 6.5.1 64-Byte Block Move With Dual Data Pointer
    • 6.5.2 64-Byte Block Move Without Dual Data Pointer
  • 6.6 Data Memory Timing
• 7. POWER MANAGEMENT
  • 7.1 Power Management Features
    • 7.1.1 Early Warning Power-Fail Interrupt
    • 7.1.2 Power-Fail Reset
    • 7.1.3 Power-On Reset
    • 7.1.4 Bandgap Select
    • 7.1.5 Watchdog Wake-Up
    • 7.1.6 Power Management Summary
  • 7.2 Power Conservation
    • 7.2.1 Idle Mode
    • 7.2.2 Stop Mode
      • 7.2.2.1 Crystal Resume from Stop Mode
    • 7.2.3 Ring Oscillator Wake-Up from Stop
      • 7.2.3.1 Speed Reduction
  • 7.3 Power Management Modes
    • 7.3.1 Power Management Mode Timing
    • 7.3.2 PMM and Peripheral Functions
    • 7.3.3 Switchback
    • 7.3.4 Clock Source Selection
    • 7.3.5 Using the Ring Oscillator
    • 7.3.6 Switching Between Clock Sources
• 8. RESET CONDITIONS
  • 8.1 Reset Sources
    • 8.1.1 Power-On/Fail Reset
    • 8.1.2 Watchdog Timer Reset
    • 8.1.3 External Reset
  • 8.2 Reset State
  • 8.3 No-Battery Reset
  • 8.4 In-System Disable Mode
• 9. INTERRUPTS
  • 9.1 Interrupt Overview
  • 9.2 Interrupt Sources
    • 9.2.1 External Interrupts
    • 9.2.2 Timer Interrupts
    • 9.2.3 Serial Communication Interrupts
    • 9.2.4 Real-Time Clock
    • 9.2.5 Power-Fail Interrupt
  • 9.3 Simulated Interrupts
  • 9.4 Interrupt Priorities
  • 9.5 Interrupt Acknowledge Cycle
  • 9.6 Interrupt Latency
  • 9.7 Interrupt Register Conflicts
• 10. PARALLEL I/O
  • 10.1 Port 0
    • 10.1.1 General-Purpose I/O
    • 10.1.2 Multiplexed Address/Data Bus AD0–AD7
  • 10.2 Port 2
    • 10.2.1 General-Purpose I/O
    • 10.2.2 Most Significant Address Byte, A8–A15
  • 10.3 Ports 1 and 3
  • 10.4 Output Functions
  • 10.5 Current-Limited Transitions
  • 10.6 Input Functions
  • 10.7 Read-Modify-Write Instructions
  • 10.8 Instruction Description
  • 10.9 I/O Port Timing
  • 10.10 Optional Functions
• 11. PROGRAMMABLE TIMERS
  • 11.1 16-Bit Timers
    • 11.1.1 Timer Mode Control Register (TMOD) Summary
    • 11.1.2 Timer/Counter Control Register (TCON) Summary
  • 11.2 Mode 0
  • 11.3 Mode 1
  • 11.4 Mode 2
  • 11.5 Mode 3
  • 11.6 Timer 2
    • 11.6.1 Timer Two Control Register (T2CON) Summary
    • 11.6.2 Timer Two Mode Control Register (T2MOD) Summary
    • 11.6.3 Timer 2 Capture Registers (RCAP2L, RCAP2H) Summary
      • 11.6.3.1 Least Significant Byte Capture of Timer 2 (RCAP2L)
      • 11.6.3.2 Most Significant Byte Capture of Timer 2 (RCAP2H)
  • 11.7 Timer 2 Modes
    • 11.7.1 16-Bit Timer/Counter
    • 11.7.2 16-Bit Timer with Capture
    • 11.7.3 16-Bit Auto-Reload Timer/Counter
    • 11.7.4 Up/Down Count Auto-Reload Timer/Counter
    • 11.7.5 Baud-Rate Generator
    • 11.7.6 Timer Output Clock Generator
  • 11.8 Time Base Selection
  • 11.9 Watchdog Timer
    • 11.9.1 Watchdog Control Register (WDCON) Summary
    • 11.9.2 Clock Control Register (CKCON) Summary
• 12. SERIAL I/O
  • 12.1 Serial Mode Summary
    • 12.1.1 Mode 0
    • 12.1.2 Mode 1
    • 12.1.3 Mode 2
    • 12.1.4 Mode 3
  • 12.2 Serial Port Initialization
    • 12.2.1 Serial Port Control 0 Register (SCON0; 98h)
    • 12.2.2 Serial Port Control 1 Register (SCON1; C0h)
    • 12.2.3 Power Control Register (PCON; 87h)
    • 12.2.4 Watchdog Control Register (WDCON; D8h)
    • 12.2.5 Timer Two Control Register ( T2CON; C8h)
  • 12.3 Baud Rates
    • 12.3.1 Mode 0
    • 12.3.2 Mode 2
    • 12.3.3 Mode 1 or 3
  • 12.4 Serial I/O Description
    • 12.4.1 Mode 0
    • 12.4.2 Mode 1
    • 12.4.3 Mode 2
    • 12.4.4 Mode 3
  • 12.5 Framing Error Detection
  • 12.6 Multiprocessor Communication
• 13. TIMED-ACCESS PROTECTION
  • 13.1 Protected Bits
  • 13.2 Protection Scheme
  • 13.3 Timed-Access Protects Watchdog
• 14. REAL-TIME CLOCK
  • 14.1 Starting and Stopping the RTC
  • 14.2 Setting and Reading the RTC Time Registers
  • 14.3 Using the RTC Alarm
  • 14.4 Using the Day of the Week Bits
  • 14.5 Choosing an RTC Crystal
  • 14.6 Calibrating the RTC Oscillator
• 15. BATTERY BACKUP
  • 15.1 Selecting a Battery
  • 15.2 Lithium Battery Considerations
• 16. INSTRUCTION SET DETAILS
• 17. TROUBLESHOOTING
  • 17.1 Device Operates at One-Third the Crystal Speed
  • 17.2 Device Resets for No Reason
  • 17.3 Access to Internal MOVX SRAM Is Unsuccessful
  • 17.4 Real-Time Clock Does Not Operate or Keep Accurate Time
  • 17.5 Serial Port Does Not Work
  • 17.6 High-Speed Microcontroller Does Not Work in Existing 8051 Design
• 18. MICROCONTROLLER DEVELOPMENT SUPPORT
  • 18.1 Technical Support
  • 18.2 Development Tools
  • 18.3 Software Compatibility
  • 18.4 High-Level Language Compilers
• 19. REVISION HISTORY