Maxim Integrated Secure Microcontroller - Manual (Page 20)

Secure Microcontroller User’s Guide
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Figure 4-2. Scratchpad Register Map
7FH
2FH 7F 7E 7D 7C 7B 7A 79 78
2EH 77 76 75 74 73 72 71 70
2DH 6F 6E 6D 6C 6B 6A 69 68
2CH 67 66 65 64 63 62 61 60
2BH 5F 5E 5D 5C 5B 5A 59 58
2AH 57 56 55 54 53 52 51 50
29H 4F 4E 4D 4C 4B 4A 49 48
28H 47 46 45 44 43 42 41 40
27H 3F 3E 3D 3C 3B 3A 39 38
26H 37 36 35 34 33 32 31 30
25H 2F 2E 2D 2C 2B 2A 29 28
24H 27 26 25 24 23 22 21 20
23H 1F 1E 1D 1C 1B 1A 19 18
22H 17 16 15 14 13 12 11 10
21H 0F 0E 0D 0C 0B 0A 09 08
20H 07 06 05 04 03 02 01 00
1FH
BANK 3
18H
17H
BANK 2
10H
0FH
BANK 1
08H
07H
BANK 0
00H
MSB LSB
4.1.2 Program and Data Memory
The secure microcontroller divides its main memory between program and data segments. Each map
consists of a 64kB area from 0000h–FFFFh. Program memory is inherently read-only, and data memory
is read/write. The CPU automatically routes program fetches to the program area and MOVX instructions
to the data memory area. All of these elements are in common with the standard 8051. Secure
microcontroller differences are in the memory interface, memory map control, and flexibility of the
memory resources.
Secure microcontrollers provide two separate buses for memory access. The first is a bytewide
address/data bus that is new to the 8051 architecture. This bus also provides a switched supply output that
makes standard SRAM into nonvolatile memory, decoded chip enables, and a R/W strobe. Furthermore,
the bytewide bus allows NV RAM memory to be divided between program and data segments. When
using a segment of the RAM as program memory, this area can be loaded using the bootstrap loader
function described later.
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