Cypress CYV15G0404DXB - Manual (Page 33)

CYV15G0404DXB
Document #: 38-02097 Rev. *B Page 33 of 44
Note
37. When operated with a half rate REFCLKx±, the setup and hold specifications for data relative to RXCLKx are relative to both rising and falling edges of the
respective clock output
Switching Waveforms for the CYV15G0404DXB HOTLink II Receiver
RXCLKx+
RXDx[7:0],
RXSTx[2:0]
t
RXDV+
t
RXDV–
t
RXCLKP
Receive Interface
Read Timing
RXRATEx = 1
RXCLKx-
Recovered Clock selected
ADDR[3:0]
t
DATAS
Bus Configuration
Write Timing
DATA[7:0]
WREN
t
DATAH
t
WRENP
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