Echelon Series 6000 Chip databook - Manual (Page 26)

Series 6000 Architecture
The main components of the architecture for a Series 6000 chip, as shown in Figure 3
include:
• CPUs — a Series 6000 chip includes three processors to manage operation of the
chip, the network, and the user application. At higher clock rates, there is also a
separate processor to handle interrupts.
• ROM — a Series 6000 chip includes 16 KB of read-only memory (ROM), which holds
the a system firmware image used for booting a system image from flash.
• RAM — a Series 6000 chip includes 64 KB of random access memory (RAM), which
stores user applications and data. The RAM is partitioned according to a logical
memory map so that the amount that is available for user applications and data is
less than 64 KB. See Memory Map for information about how the RAM is configured.
• Serial memory interface — this interface manages the external non-volatile memory
(NVM) using the serial peripheral interface (SPI).
• Communications port — the communications port provides network access for the
chip. For an FT 6000 Smart Transceiver, this port connects to an FT-X3
Communications Transformer. For a Neuron 6000 Processor, this port connects to an
external transceiver.
• I/O — 12 dedicated I/O pins (see Characteristics of the Digital Pins).
• Clock, reset, and service — on-chip clock, phase-locked loop (PLL), reset, and service-
pin functions.
• JTAG — a Series 6000 chip includes a JTAG (IEEE 1149.1) interface for boundary
scan operations. See JTAG Interface.
The pinout labels shown in Figure 3 are described in Pin Assignments.
14 Hardware Resources