Document Outline

• ATCA-7365-CE
• Contents
• About this Manual
  • Overview of Contents
  • Abbreviations
  • Conventions
  • Summary of Changes
• Safety Notes
  • EMC
  • Installation
  • Operation
  • Switch Settings
  • Battery
  • Environment
• Sicherheitshinweise
  • EMV
  • Installation
  • Betrieb
  • Schaltereinstellungen
  • Batterie
  • Umweltschutz
• Introduction
  • 1.1 Features
  • 1.2 Standard Compliances
  • 1.3 Mechanical Data
  • 1.4 Product Identification
  • 1.5 Ordering Information
• Hardware Preparation and Installation
  • 2.1 Unpacking and Inspecting the Blade
  • 2.2 Environmental and Power Requirements
    • 2.2.1 Environmental Requirements
    • 2.2.2 Power Requirements
  • 2.3 Blade Layout
  • 2.4 Switch Settings
  • 2.5 Installing the Blade Accessories
    • 2.5.1 DIMM Memory Modules
    • 2.5.2 PMEM and SATA Module
    • 2.5.3 USB 2.0 Flash Module
  • 2.6 Installing and Removing the Blade
    • 2.6.1 Installing the Blade
    • 2.6.2 Removing the Blade
• Controls, Indicators, and Connectors
  • 3.1 Mechanical Layout
  • 3.2 Face Plate
    • 3.2.1 LEDs
    • 3.2.2 Keys
    • 3.2.3 Connectors
      • 3.2.3.1 Ethernet Connector
      • 3.2.3.2 Serial Interface Connector
      • 3.2.3.3 USB Connectors
      • 3.2.3.4 VGA-7360 Module Connector
  • 3.3 On-board Connectors
    • 3.3.1 PMEM/SFMEM Module Connector
    • 3.3.2 USB Flash Module Connector
  • 3.4 AdvancedTCA Backplane Connectors
• BIOS
  • 4.1 Introduction
  • 4.2 Accessing the Blade Using the Serial Console Redirection
    • 4.2.1 Requirements for Serial Console Redirection
    • 4.2.2 Default Access Parameters
    • 4.2.3 Connecting to the Blade
  • 4.3 Changing Configuration Settings
  • 4.4 Boot Options
    • 4.4.1 Supported Boot Devices
    • 4.4.2 Selecting The Boot Device
    • 4.4.3 By Boot Selection Menu
    • 4.4.4 iSCSI Setup for Base and Fabric Ethernet
      • 4.4.4.1 ISCSI Port Selection
      • 4.4.4.2 iSCSI Port Configuration
      • 4.4.4.3 iSCSI Boot Configuration
      • 4.4.4.4 iSCSI Challenge Handshake Authentication Protocol (CHAP) Configuration
  • 4.5 BIOS Setup Configuration
    • 4.5.1 Main
    • 4.5.2 Advanced
      • 4.5.2.1 Advanced -> CPU Configuration
      • 4.5.2.2 Advanced -> Memory Configuration
      • 4.5.2.3 Advanced -> Chipset - North Bridge
      • 4.5.2.4 Advanced -> Chipset - South Bridge
      • 4.5.2.5 Advanced -> SATA Configuration
      • 4.5.2.6 Advanced -> USB Configuration
      • 4.5.2.7 Advanced -> Super IO Configuration
      • 4.5.2.8 Advanced -> Serial Port Console Redirection
      • 4.5.2.9 Advanced -> UEFI Network Stack
      • 4.5.2.10 Advanced -> Runtime Error Logging
      • 4.5.2.11 Advanced -> SMBIOS Event Log
      • 4.5.2.12 Advanced -> Local IPMI System Event Log
      • 4.5.2.13 Advanced -> WHEA Configuration
    • 4.5.3 IPMI
      • 4.5.3.1 IPMI -> IPMI Watchdog Configuration
      • 4.5.3.2 IPMI -> System Event Log
    • 4.5.4 iSCSI
    • 4.5.5 Boot
      • 4.5.5.1 Boot -> Option ROM Execution
    • 4.5.6 Security
    • 4.5.7 Save & Exit
  • 4.6 CPU Performance Settings
  • 4.7 Memory Configuration
    • 4.7.1 Independent Channel Mode
    • 4.7.2 Spare Channel Mode
    • 4.7.3 Mirrored Channel Mode
    • 4.7.4 Lockstep Channel Mode
  • 4.8 Restoring BIOS Default Settings
  • 4.9 Shelf Slot Power Requirement
  • 4.10 LED Usage
  • 4.11 Upgrading the BIOS
  • 4.12 BIOS Error Logging
    • 4.12.1 Runtime Error Logging
    • 4.12.2 Error Simulation
    • 4.12.3 IPMI Error Logging
    • 4.12.4 SMBIOS Error Logging
      • 4.12.4.1 Single-bit ECC Memory Error
      • 4.12.4.2 Multi-bit ECC Memory Error
      • 4.12.4.3 POST Error
      • 4.12.4.4 PCI Parity Error
      • 4.12.4.5 PCI System Error
      • 4.12.4.6 CPU Failure
      • 4.12.4.7 Correctable Memory Log Disabled
      • 4.12.4.8 Log Area Reset/Cleared
      • 4.12.4.9 System Boot
      • 4.12.4.10 OEM Event EFI Status Code
  • 4.13 BIOS Status Codes
    • 4.13.1 Status Code Ranges
    • 4.13.2 Standard Status Codes
• Functional Description
  • 5.1 Block Diagram
  • 5.2 Processor
  • 5.3 Memory
    • 5.3.1 Persistent memory (PMEM Module)
  • 5.4 Chipset
  • 5.5 I/O Controller
  • 5.6 Firmware Flashes
  • 5.7 Ethernet Ports
  • 5.8 Storage Controller
  • 5.9 Embedded Flash Disk
    • 5.9.1 SATA Embedded Flash Solid State Disc (SSD)
  • 5.10 BIOS
  • 5.11 IPMC
  • 5.12 Serial Redirection
  • 5.13 Serial over LAN
  • 5.14 Control Logic
  • 5.15 Front Board Face Plate
  • 5.16 USB 2.0 Interface
  • 5.17 SMBus Interface
  • 5.18 Real Time Clock
  • 5.19 VGA Module
    • 5.19.1 2D Graphics Engine
    • 5.19.2 Supported VGA graphics modes:
• Maps and Registers
  • 6.1 Interrupt Structure
  • 6.2 PCI Express Port Mapping
  • 6.3 Registers
    • 6.3.1 Register Decoding
      • 6.3.1.1 LPC Decoding
      • 6.3.1.2 SPI Register Decoding
    • 6.3.2 POST Code Register
    • 6.3.3 Super IO Configuration Register
      • 6.3.3.1 Entering the Configuration State
      • 6.3.3.2 Configuration Mode
      • 6.3.3.3 Super IO Configuration Registers
    • 6.3.4 UART1 and UART2 Register Map
      • 6.3.4.1 UART Register Overview
      • 6.3.4.2 UART Registers DLAB=0
      • 6.3.4.3 Programmable Baud Rate Generator
  • 6.4 FPGA Register Mapping
    • 6.4.1 LPC I/O Register Map
    • 6.4.2 IPMC SPI Register Map
    • 6.4.3 Module Identification Register
    • 6.4.4 Version Register
    • 6.4.5 Serial Redirection Control Register
    • 6.4.6 Serial over LAN (SOL) Control Register
    • 6.4.7 Serial Line Routing Register
    • 6.4.8 IPMC Power Level Register
    • 6.4.9 SPD PROM MUX Control Register
    • 6.4.10 Reset Registers
      • 6.4.10.1 BIOS Reset Source Register
      • 6.4.10.2 Reset Mask Register
      • 6.4.10.3 BIOS IPMC Watchdog Timeout Register
      • 6.4.10.4 BIOS Push Button Enable Register
      • 6.4.10.5 OS Reset Source Register
      • 6.4.10.6 OS IPMC Watchdog Timeout Register
      • 6.4.10.7 IPMC Watchdog Timeout Register
      • 6.4.10.8 IPMC Reset Source Register
    • 6.4.11 RTM SPI Interface Registers
    • 6.4.12 Interrupt Control and Status Registers
      • 6.4.12.1 RTM Interrupt Status Register
      • 6.4.12.2 External Interrupt Status Register
      • 6.4.12.3 Processor Hot Status/Control Register
      • 6.4.12.4 Telecom Status/Control Register
      • 6.4.12.5 Interrupt Mask and Map Registers
    • 6.4.13 Flash Status and Protection Registers
    • 6.4.14 BIOS Boot Mode Register
    • 6.4.15 SFMEM Module Configuration Register
    • 6.4.16 Update Channel Equalization Control Register
    • 6.4.17 IPMC E-Keying Status Register
    • 6.4.18 IPMC E-Keying Control Register
    • 6.4.19 IPMC GPIO Register
    • 6.4.20 LED Status and Control Register
    • 6.4.21 NMI Status and Control Register
    • 6.4.22 Telecom Clock Supervision Registers
      • 6.4.22.1 Telecom Clocking Status Registers
      • 6.4.22.2 Telecom Timer Registers
    • 6.4.23 Miscellaneous Status/Control Registers
    • 6.4.24 Scratch Registers
• Serial Over LAN
  • 7.1 Overview
  • 7.2 Installing the ipmitool
  • 7.3 Configuring SOL Parameters
    • 7.3.1 Using Standard IPMI Commands
    • 7.3.2 Using ipmitool
  • 7.4 Establishing a SOL Session
• Supported IPMI Commands
  • 8.1 Standard IPMI Commands
    • 8.1.1 Global IPMI Commands
    • 8.1.2 System Interface Commands
    • 8.1.3 Watchdog Commands
    • 8.1.4 SEL Device Commands
    • 8.1.5 FRU Inventory Commands
    • 8.1.6 Sensor Device Commands
    • 8.1.7 Chassis Device Commands
      • 8.1.7.1 System Boot Options Commands
    • 8.1.8 LAN Device Commands
  • 8.2 PICMG 3.0 Commands
    • 8.2.1 Set/Get Power Level
  • 8.3 Artesyn Embedded Technologies Specific Commands
    • 8.3.1 Serial Output Commands
      • 8.3.1.1 Set Serial Output Command
      • 8.3.1.2 Get Serial Output Command
  • 8.4 Pigeon Point Specific Commands
    • 8.4.1 Get Status Command
    • 8.4.2 Get Serial Interface Properties Command
    • 8.4.3 Set Serial Interface Properties Command
    • 8.4.4 Get Debug Level Command
    • 8.4.5 Set Debug Level Command
    • 8.4.6 Get Hardware Address Command
    • 8.4.7 Set Hardware Address Command
    • 8.4.8 Get Handle Switch Command
    • 8.4.9 Set Handle Switch Command
    • 8.4.10 Get Payload Communication Time-Out Command
    • 8.4.11 Set Payload Communication Time-Out Command
    • 8.4.12 Enable Payload Control Command
    • 8.4.13 Disable Payload Control Command
    • 8.4.14 Reset IPMC Command
    • 8.4.15 Hang IPMC Command
    • 8.4.16 Graceful Reset Command
    • 8.4.17 Get Payload Shutdown Time-Out Command
    • 8.4.18 Set Payload Shutdown Time-Out Command
    • 8.4.19 Get Module State Command
    • 8.4.20 Enable Module Site Command
    • 8.4.21 Disable Module Site Command
    • 8.4.22 Reset Carrier SDR Repository Command
• FRU Information and Sensor Data Records
  • 9.1 FRU Information
  • 9.2 MAC Address Record
  • 9.3 E-Keying
  • 9.4 Power Configuration
  • 9.5 Sensor Data Records
• Firmware Upgrade
  • 10.1 HPM.1 Firmware Upgrade
    • 10.1.1 Overview
    • 10.1.2 Installing the Ipmitool
      • 10.1.2.1 Update Procedure
    • 10.1.3 Interface
      • 10.1.3.1 KCS Interface
      • 10.1.3.2 IPMB-0
      • 10.1.3.3 IPMI over LAN (BASE)
  • 10.2 IPMC Upgrade
  • 10.3 BIOS/FPGA Upgrade
  • 10.4 Upgrade Package
• A Replacing the Battery
  • A.1 Replacing the Battery
• B Related Documentation
  • B.1 Artesyn Embedded Technologies - Embedded Computing Documentation
  • B.2 Manufacturers’ Documents
  • B.3 Related Specifications