BECKHOFF EtherCAT IPCore Section III User Manual
And xilinx
Advertising
Version 2.1
Date:
2015-05-12
Hardware Data Sheet Section III Addendum
ET1810 / ET1811 / ET1812 and ET1815 / ET1816
Slave Controller
IP Core for Altera
®
and Xilinx
®
FPGAs
Section I
– Technology
(Onli
Section II
– Register Description
(Onli
Section III
– Hardware Description
(Onli
Section III
– Addendum
Design Flow Compatibility, FPGA Device Support, Known issues
Advertising
Table of contents
Document Outline
- Section III – Addendum
- 1 Overview
- 2 EtherCAT IP Core for Altera FPGAs
- 3 EtherCAT IP Core for Xilinx FPGAs
- 3.1 FPGA design tool compatibility
- 3.2 FPGA device compatibility
- 3.3 Known Designflow Issues
- 3.3.1 General Vivado issues
- 3.3.2 Vivado 2015
- 3.3.2.1 Vivado 2015.1: The resource consumption (Slice LUTs) of the EtherCAT IP Core is too high
- 3.3.2.2 Vivado 2015.1: ZC702_AXI_VIVADO example design invalid constraints
- 3.3.2.3 Vivado 2015.1: ZC702_AXI_VIVADO example design does not meet timing requirements
- 3.3.2.4 Vivado 2015.1: ZC702_AXI_VIVADO example design and EtherCAT IP cores outside the Zynq block design fails in SDK
- 3.3.3 Vivado 2014
- 3.3.3.1 Vivado 2014.4: ZC702_AXI_VIVADO example design and EtherCAT IP cores outside the Zynq block design fails in SDK
- 3.3.3.2 Vivado 2014.3: Abnormal program termination (EXCEPTION_ACCESS_VIOLATION)
- 3.3.3.3 Vivado until 2014.3: Tri-state buffers inside EtherCAT IP Core
- 3.3.3.4 Vivado until 2014.2: The resource consumption of the EtherCAT IP Core is too high
- 3.3.3.5 Vivado until 2014.1: The ZC702 AXI Vivado example design is not synthesizable
- 3.3.4 Vivado 2013
- 3.3.5 ISE/EDK/PlanAhead 14.7
- 4 Appendix