Measurement Computing PCM-DAS16x/16 - Manual (Page 15)

Here is where the design of the analog front end is critical to maintaining total
throughput. Every A/D chip has a fixed input range, typically +/-5V. It is the analog
front end that amplifies low level signals and adjusts unipolar signals to match the
A/D converter's standard input.
A poorly designed analog front end will show up very quickly in the throughput speci-
fications. If you see that an A/D board has high throughput in only one or two ranges
but is slowed greatly at all other ranges, you are seeing the practical implications of a
poor front end design. The PCM-DAS16x/16 achieves 100KHz in all of the four
ranges.
4.3 TRIGGERING & TRANSFER
A Trigger is the event that begins an acquisition/transfer cycle. There are three ways
to trigger a PCM-DAS16x/16; programmable pacer, software or external. The trig-
ger source is programmable. The programmable pacer is the product of two 16 bit
counters dividing a 10MHz or 1MHz wave derived from a 10MHz XTAL which may
be used to trigger any number of paced conversions. A single conversion may be trig-
gered by software at any time. External trigger, pacer clock and interrupt signals may
also be used to control conversions and synchronize to external events.
Once a conversion is made the sample is placed into a 512 sample FIFO buffer from
which it may be retrieved one sample at a time or in blocks via REP-INSW transfers.
How do FIFO size and design affect throughput?
The FIFO buffer stores samples from the A/D converter as they are being converted.
When a block of samples is ready and when the PC is ready, the FIFO is emptied into
system memory. A properly designed FIFO of the correct size is a requirement for
Windows, or samples will be lost at all but the slowest speeds.
Design of the FIFO is critical. Simply having a FIFO is not enough. Most FIFO
designs employ a half-full transfer initiation circuit. When the FIFO is half full, the
transfer request is made. Samples continue to fill the second half of the FIFO while
the CPU responds to the transfer request and transfers data to system memory.
Some other manufacturer's boards have only a 'FIFO full' circuit. What do you think
happens to samples taken after the FIFO is full while waiting for the CPU to begin
unloading the FIFO?
FIFO size is critical also. We have seen boards with FIFOs as small as 16 samples.
The PCM-DAS16x/16 has a 512 sample FIFO buffer! A size we have determined
through extensive testing to be a requirement for real situations.
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