Grass Valley 8950ADC - Manual (Page 41)

8950ADC Instruction Manual 41
Functional Description
Input Phase Lock Loop (PLL) and 54 MHz clock generator
From the incoming composite sync, the PLL generates a 54 MHz clock for
oversampling. This clock also servers as a free-running clock when no
input signal is present.
Delay line
The on board delay line provides a maximum 2.5 line signal delay. The
delay time is under user control in 37 ns increments.
Serializer
The Serializer is a standard D1, 10-bit, 270 MHz serializer with embedded
Error Data Handling.
Embedded processor
The embedded processor provides the interface between the user and all
the processing logic of the 8950ADC, as well as communication between
the 8950ADC and a remote host processor.