Lanner VES-220 - Manual (Page 13)

10
Motherboard Information
Chapter 3
Embedded and Industrial Computing
Signal PIN PIN Signal
GND A80 B80 GND
LVDS_A_CK+ A81 B81 LVDS_B_CK+
LVDS_A_CK- A82 B82 LVDS_B_CK-
LVDS_I2C_CK A83 B83 LVDS_BKLT_CTRL
LVDS_I2C_DAT A84 B84 VCC_5V_SBY_1
GPI3 A85 B85 VCC_5V_SBY_2
KBD_RST# A86 B86 VCC_5V_SBY_3
KBD_A20GATE A87 B87 VCC_5V_SBY_4
PCIE_CK_REF0+ A88 B88 RSVD5
PCIE_CK_REF0-- A89 B89 VGA_RED
GND A90 B90 GND
RSVD1 A91 B91 VGA_GRN
RSVD2 A92 B92 VGA_BLU
GPO0 A93 B93 VGA_HSYNC
RSVD3 A94 B94 VGA_VSYNC
RSVD4 A95 B95 VGA_I2C_CK
GND A96 B96 VGA_I2C_DAT
NC A97 B97 SPI CS#
NC A98 B98 NC
NC A99 B99 NC
GND A100 B100 GND
NC A101 B101 NC
NC A102 B102 NC
NC A103 B103 NC
VCC_12V A104 B104 VCC_12V
VCC_12V A105 B105 VCC_12V
VCC_12V A106 B106 VCC_12V
VCC_12V A107 B107 VCC_12V
VCC_12V A108 B108 VCC_12V
VCC_12V A109 B109 VCC_12V
GND A110 B110 GND
Signal Descriptions of the CN1A:
Audio •
Signal Signal Description
AC_SYNC HD Audio Sync
AC_RST# HD Audio Reset
AC_SDIN[0:2] Audio CODEC Serial Data
AC_BITCLK HD Audio Clock
AC_SDOUT HD Audio Data
Gigabit Ethernet Signals •
Signal Signal Description
GBE0_MD[0:3]
+/-
Gigabit Ethernet Controller 0: Media
Dependent Interface Differential Pairs
0,1,2,3. The MDI can operate in 1000,
100 and 10 Mbit/sec modes. Some
pairs are unused in some modes, per
the following:
1000B-T 100B-T 10B-T
MDI[0]+/- B1_DA+/ TX+/- TX+/-
MDI[1]+/ B1_DB+/ RX+/- RX+/-
MDI[2]+/ B1_DC+/ X X
MDI[3]+/ B1_
DD+/
X X
GBE0_ACT# Gigabit Ethernet Controller 0 activity
indicator, active low.
GBE0_Link# Gigabit Ethernet Controller 0 link indi-
cator, active low.
GBE0_Link100# Gigabit Ethernet Controller 0 100 Mbit
/sec link indicator, active low.
GBE0_Lin1000# Gigabit Ethernet Controller 0 1000
Mbit/sec link indicator, active low.
GPIO Signals •
Signal Signal Description
GPI[0:4] General purpose input pins.
GPO[0:4] General purpose output pins.
Flat Panel LVDS Signals •
Signal Signal Description
BIASON Controls panel contrast voltage.
DIGON Controls panel digital power.
ENBKL# Controls backlight power enable.
I 2 C_DAT,
I 2 C_CLK
I 2 C interface for panel parameter EEPROM.
This EERPOM is mounted on the LVDS
receiver. The data in the EEPROM allows
the EXT module to automatically set the
proper timing parameters for a specific
LCD panel.
LPC Signals •
Signal Signal Description
LPC_FRAME# LPC frame indicates the start of an LPC
cycle
LPC_AD[0:3] LPC multiplexed address, command and
data bus
LPC_
DRQ[0:1]#
LPC serial DMA request
LPC_CLK LPC clock output - 33MHz nominal
LPC_SERIRQ LPC serial interrupt