Appendix b, Appendix, Ep-3vwm – EPoX Computer EP-3VWM User Manual
Page 51: B-1 post codes for bios 6.0 code
Appendix
B-1
EP-3VWM
Appendix B
B-1 POST CODES
For BIOS 6.0 Code
POST (hex)
DESCRIPTION
CFh
Test CMOS R/W functionality.
C0h
Early chipset initialization:
- Disable shadow RAM
- Disable L2 cache (socket 7 or below)
- Program basic chipset registers
C1h
Detect memory
- Auto-detection of DRAM size, type and ECC.
- Auto-detection of L2 cache (socket 7 or below)
C3h
Expand compressed BIOS code to DRAM
C5h
Call chipset hook to copy BIOS back to E000 & F000
shadow RAM.
0h1
Expand the Xgroup codes locating in physical address
1000:0
02h
Reserved
03h
Initial Superio_Early_Init switch.
04h
Reserved
05h
1. Blank out screen
2. Clear CMOS error flag
06h
Reserved
07h
1. Clear 8042 interface
2. Initialize 8042 self-test
08h
1. Test special keyboard controller for Winbond 977
series Super I/O chips.
2. Enable keyboard interface.
09h
Reserved
0Ah
1. Disable PS/2 mouse interface (optional).
2. Auto detect ports for keyboard & mouse followed by
a port & interface swap (optional).