Motorola MPC5200 - Manual (Page 16)

10 KADAK KwikNet MPC5200 FEC Device Driver
6.3 MPC5200 Interrupt Exceptions
The PowerPC MPC5200 interrupt management subsystem is incredibly complex. All
device interrupt sources are funneled through three PowerPC exceptions in the processor
Exception Vector Table. Normal interrupt sources are vectored to the external interrupt
exception at offset
0x0500 . Critical interrupts, including all interrupt requests generated
by the BestComm DMA Engine, are vectored to the critical interrupt exception at offset
0x0A00 . Other internal interrupt sources are vectored to the system management
exception at offset 0x1400 .
Assembly language code must be installed in each of these exception vectors to handle
the exception, determine the source of the interrupt which initiated the exception and
service the interrupt source.
A further complication arises because the critical interrupt exception cannot be masked
off. Hence, a critical interrupt exception from a BestComm interrupt request can preempt
service of a normal interrupt exception or a system management exception.
If you are not familiar with the PowerPC architecture, its exception handling rules, its
interrupt controller operation and PowerPC assembly language programming, writing
exception handler code can be a daunting task. In fact, the complexity provides a good
reason to use an RTOS such as KADAK's AMX PPC
32 kernel which services these
exceptions for you.
Operation with AMX PPC 32
Included with AMX PPC 32 is a board support module LITE5200.S for the Motorola
Lite5200 Evaluation Board. Board initialization function chbrdinit() within this
module is called prior to launching AMX. This function programs the MPC5200
interrupt controller to reroute the critical interrupt exception from offset
0x0A00 to the
external interrupt exception at offset 0x0500 . Doing so resolves the interrupt nesting
issue introduced by the non-maskable critical interrupt exception.
Also included in the AMX MPC5200 board support module is the AMX Interrupt
Identification Procedure
ch500vd() which decodes the interrupt source and vectors
through the linear AMX Vector Table to the device specific ISP root. The ISP root calls
the ISP stem to dismiss the interrupt request and, if necessary, signal that the ISP Handler
is to be executed as soon as possible by the AMX Interrupt Supervisor.
Interrupt Identification Procedure ch500vd() maps the interrupt sources which generate
an external interrupt exception, a critical interrupt exception or a system management
exception to a single block of 84 vectors within the AMX Vector Table. Interrupt
Identification Procedure
ch500vd() must be used for each of the three MPC5200
exceptions.