Motorola M68HC08 - Manual (Page 105)

Software Design
Implementation Notes
DRM028 — Rev 0 Designer Reference Manual
MOTOROLA Software Design 105
PVAL6L registers. Then the back-EMF zero crossing selection set is
provided by setting PORTF according to V_MUX variable.
5.6.3 BLDC Speed Control and Calculation
Desired speed calculation and PWM duty cycle setting is quite simple,
but there are some C language syntax tricks. Also, the scaling aspect
needs to be taken into consideration.
5.6.3.1 Desired Speed Calculation
The 8 bit value Speed_Desired is calculated using 8-bit multiplication of
two 8-bit variables, Sp_Input and Coef_Speed_Inp. The syntax is:
(unsigned char)((Sp_Input*Coef_Speed_Inp)>>8)
This syntax is used to generate optimal code using the MUL instruction.
5.6.3.2 PWM Duty Cycle
PWM duty cycle is set for all six PWM channels according to regulators
output OutReg_U8. The maximal duty cycle is at OutReg_U8 = 255.
The registers PVAL1H, PVAL1L through PVAL6H, PVAL6L are set
proportionally to the PWM modulus register PMOD =
MCPWM_MODULUS constant (100% duty cycle is when PVALx =
PMOD).
The PWM_Val_Max variable is:
PWM_Val_Max = DUTY_PWM_MAX*MCPWM_MODULUS
This variable is used for scaling of the regulator output OutReg_U8. The
registers PVAL1H, PVAL1L through PVAL6H, PVAL6L are loaded with
PWM_Val calculated from OutReg_U8:
PWM_Val = PWM_Val_Max*OutReg_U8/256
This calculation is provided with macro umul_16x8_macro.
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Freescale Semiconductor, Inc.
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