Intel 21555 - Manual (Page 6)

6 21555 Non-Transparent PCI-to-PCI Bridge User Manual
Contents
16.7 Interrupt Registers ............................................................................................................ 170
16.8 Scratchpad Registers ....................................................................................................... 174
16.9 PROM Registers............................................................................................................... 175
16.10 SROM Registers............................................................................................................... 179
16.11 Arbiter Control................................................................................................................... 183
16.12 Error Registers.................................................................................................................. 183
16.13 Init Registers..................................................................................................................... 185
16.14 JTAG Registers ................................................................................................................ 190
16.15 VPD Registers .................................................................................................................. 192
Index ..................................................................................................................................................... 197
Figures
1 21555 Intelligent Controller Application ...................................................................................... 16
2 21555 Microarchitecture ............................................................................................................. 19
3 BAR Setup Register Example .................................................................................................... 35
4 Address Format .......................................................................................................................... 36
5 Direct Offset Address Translation............................................................................................... 37
6 Downstream Address Translation Example ............................................................................... 37
7 Address Translation Using A Lookup Table ............................................................................... 39
8 Upstream Lookup Table Address Translation ............................................................................ 40
9 Lookup Table Entry Format ........................................................................................................ 41
10 Dual-Address Transaction Forwarding ....................................................................................... 42
11 CompactPCI Hot-Swap Connections ......................................................................................... 73
12 21555 Hot-Swap Insertion and Removal .................................................................................... 75
13 Synchronous Secondary Clock Generation................................................................................ 78
14 Parallel and Serial ROM Connections ........................................................................................ 84
15 PROM Read Timing ................................................................................................................... 85
16 PROM Write Timing.................................................................................................................... 87
17 Read and Write Strobe Timing ................................................................................................... 88
18 Attaching Multiple Devices on the ROM Interface ...................................................................... 90
19 SROM Write All Timing Diagram ................................................................................................ 94
20 SROM Write Enable Timing Diagram ......................................................................................... 94
21 SROM Write Disable Timing Diagram ........................................................................................ 94
24 SROM Check Status Timing Diagram ........................................................................................ 95
22 SROM Erase Timing Diagram .................................................................................................... 95
23 SROM Erase All Operation......................................................................................................... 95
25 Secondary Arbiter Example ........................................................................................................ 99
26 Signal trst_l States.................................................................................................................... 112
Tables
1 Signal Type Abbreviations.......................................................................................................... 13
2 Register Abbreviations ............................................................................................................... 14
3 21555 and PPB Feature Comparison......................................................................................... 17
4 Decoded and Not Decoded Addresses ...................................................................................... 20
5 Signal Pin Functional Groups ..................................................................................................... 23
6 Primary PCI Bus Interface Signals ............................................................................................. 24