Intel 21555 - Manual (Page 7)

21555 Non-Transparent PCI-to-PCI Bridge User Manual 7
Contents
7 Primary PCI Bus Interface 64-Bit Extension Signals .................................................................. 26
8 Secondary PCI Bus Interface Signals.........................................................................................28
9 Secondary PCI Bus Interface 64-Bit Extension Signals ............................................................. 30
10 Miscellaneous Signals ................................................................................................................ 31
11 Upstream Memory 2 Window Size ............................................................................................. 38
12 Bar Summary.............................................................................................................................. 47
13 Delayed Write Transaction Target Termination Returns ............................................................ 55
14 Delayed Read Transaction Target Termination Returns ............................................................ 56
15 Prefetch Boundaries ...................................................................................................................58
16 21555 Transaction Ordering Rules............................................................................................. 62
17 Power Management, Hot-Swap, and Reset Signals................................................................... 65
18 Reset Mechanisms ..................................................................................................................... 67
19 Power Management Actions....................................................................................................... 71
20 Primary and Secondary PCI Bus Clock Signals ......................................................................... 77
21 PROM Interface Signals ............................................................................................................. 82
22 SROM Interface Signals ............................................................................................................. 91
23 Primary PCI Bus Arbitration Signals ........................................................................................... 97
24 Secondary PCI Bus Arbitration Signals ...................................................................................... 97
25 Arbiter Control Register ............................................................................................................ 100
26 Primary and Secondary PCI Bus Interrupt Signals...................................................................101
27 Primary PCI Bus Error Signals ................................................................................................. 105
28 Secondary PCI Bus Arbitration Signals .................................................................................... 106
29 Parity Error Responses............................................................................................................. 107
30 JTAG Signals............................................................................................................................ 111
31 Register Cross Reference Table .............................................................................................. 121
32 Configuration Space Address Register..................................................................................... 122
33 CSR Address Map .................................................................................................................... 126
34 Primary CSR and Downstream Memory 0 Bar ......................................................................... 130
35 Secondary CSR Memory BARs................................................................................................ 131
36 Primary and Secondary CSR I/O Bars ..................................................................................... 132
37 Downstream I/O or Memory 1 and Upstream I/O or Memory 0 BAR........................................ 133
38 Downstream Memory 2 and 3 BAR, and Upstream Memory 1 BAR ........................................ 134
39 Upper 32 Bits Downstream Memory 3 Bar ............................................................................... 135
40 Upstream Memory 2 Bar........................................................................................................... 135
41 Downstream I/O or Memory 1 and Upstream I/O or Memory 0 Translated Base Register ...... 136
42 Downstream Memory 0, 2, 3, and Upstream Memory 1 Translated Base Register ................. 137
43 Downstream I/O or Memory 1 and Upstream I/O or Memory 0 Setup Registers ..................... 138
44 Downstream Memory 0, 2, 3, and Upstream Memory 1 Setup Registers ................................ 139
45 Upper 32 Bits Downstream Memory 3 Setup Register .............................................................140
46 Downstream and Upstream Configuration Address Registers ................................................. 141
47 Downstream Configuration Data and Upstream Configuration Data Registers........................ 142
48 Configuration Own Bits Register............................................................................................... 142
49 Configuration CSR.................................................................................................................... 143
50 Downstream I/O Address and Upstream I/O Address Registers.............................................. 144
51 Downstream I/O Data and Upstream I/O Data Registers ......................................................... 145
52 I/O Own Bits Registers ............................................................................................................. 145
53 I/O CSR .................................................................................................................................... 146
54 Lookup Table Offset Register ................................................................................................... 146
55 Lookup Table Data Register ..................................................................................................... 147
56 Upstream Memory 2 Lookup Table .......................................................................................... 147