Inova High Performance CPU board ICP-PII - Manual (Page 14)

©2002 Inova Computers GmbH Page 1-4 Doc. PD00581013.004
Product Overview ICP-PIII
1.1 Specifications
Processor Socket 370 BGA (mobile) or FC-PGA based Intel Pentium III or Celeron
Pentium III Up to 1000MHz
(100MHz PSB, 256kByte L2 cache)
Mobile PIII Up to 700MHz BGA2 package with interposer
(100MHz PSB, 256kByte L2 cache)
Mobile Celeron BGA2 package with interposer
(100Mz PSB, 128kByte L2 cache)
L2 Cache 128/256kByte L2 cache depending on processor
Memory 128MByte soldered synchronous DRAM with optional BIOS activated
ECC feature. Additional Piggyback provides additional 128MByte,
or 384MByte
FLASH-Disk Available as an option (Disk-on-Chip™) providing up to 500MByte FLASH
Battery Lithium cell for RTC (NV-RAM) with a lifetime > 8 years
North Bridge 440BX North Bridge 82443BX supporting:
Ī
100MHz system bus DRAM controller with 64bit, 100MHz
SDRAM interface
Ī ECC support
Ī AGP 2X interface (66/133MHz)
Ī Power management
South Bridge M1543C:
Ī PCI/ISA Bridge
Ī Super I/O: 1 Floppy Disk Controller, 1 Parallel Port, 2 Serial Ports
Ī Fast IR
Ī IDE Controller (4 devices)
Ī Ultra 66 DMA support
Ī 12Mbit/s USB controller
Ī Interrupt controller
Ī Power Management Unit
Ī Full support for ACPI and OS directed power management
Ī
Mouse & keyboard controller
Graphics Lynx3DM or Radeon VE graphic accelerator
Ī
8/16Mbyte SGRAM/SDRAM
Ī
3D graphics, DVD & MPEG-2 support
Ī
Multi-Display
Ī
Dual View support under Microsoft Windows ® 9x, Windows ® NT ®
& Windows ® 2000
Ī
CRT / TFT resolutions up to 2048x1536
Ī
GigaST Ȣ R / PanelLink™ or TFT Piggyback
Dual display option or TFT will require dedicated front-panel.
Recovery BIOS FLASH Recovery BIOS
Watchdog Programmable up to 10 minutes; issues NMI or Reset