Silicon Laboratories C8051F347 - Manual (Page 39)

Rev. 1.3 39
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
L1 0.00 — 0.15
aaa — — 0.15
bbb — — 0.10
ddd — — 0.05
eee — — 0.08
Table 4.6. QFN-32 Package Dimensions (Continued)
Dimension Min Nom Max
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220,
variation VHHD except for custom features D2, E2, and L which are
toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.