Silicon Laboratories C8051F347 User Manual
Page 84
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
84
Rev. 1.3
P1MDIN
0xF2
Port 1 Input Mode Configuration
P1MDOUT
0xA5
Port 1 Output Mode Configuration
P1SKIP
0xD5
Port 1 Skip
P2
0xA0
Port 2 Latch
P2MDIN
0xF3
Port 2 Input Mode Configuration
P2MDOUT
0xA6
Port 2 Output Mode Configuration
P2SKIP
0xD6
Port 2 Skip
P3
0xB0
Port 3 Latch
P3MDIN
0xF4
Port 3 Input Mode Configuration
P3MDOUT
0xA7
Port 3 Output Mode Configuration
P3SKIP
0xDF
Port 3Skip
P4
0xC7
Port 4 Latch
P4MDIN
0xF5
Port 4 Input Mode Configuration
P4MDOUT
0xAE
Port 4 Output Mode Configuration
PCA0CN
0xD8
PCA Control
PCA0CPH0
0xFC
PCA Capture 0 High
PCA0CPH1
0xEA
PCA Capture 1 High
PCA0CPH2
0xEC
PCA Capture 2 High
PCA0CPH3
0xEE
PCA Capture 3High
PCA0CPH4
0xFE
PCA Capture 4 High
PCA0CPL0
0xFB
PCA Capture 0 Low
PCA0CPL1
0xE9
PCA Capture 1 Low
PCA0CPL2
0xEB
PCA Capture 2 Low
PCA0CPL3
0xED
PCA Capture 3 Low
PCA0CPL4
0xFD
PCA Capture 4 Low
PCA0CPM0 0xDA
PCA Module 0 Mode Register
PCA0CPM1 0xDB
PCA Module 1 Mode Register
PCA0CPM2 0xDC
PCA Module 2 Mode Register
PCA0CPM3 0xDD
PCA Module 3 Mode Register
PCA0CPM4 0xDE
PCA Module 4 Mode Register
PCA0H
0xFA
PCA Counter High
PCA0L
0xF9
PCA Counter Low
PCA0MD
0xD9
PCA Mode
PCON
0x87
Power Control
PFE0CN
0xAF
Prefetch Engine Control
PSCTL
0x8F
Program Store R/W Control
PSW
0xD0
Program Status Word
REF0CN
0xD1
Voltage Reference Control
REG0CN
0xC9
Voltage Regulator Control
RSTSRC
0xEF
Reset Source Configuration/Status
SBCON1
0xAC
UART1 Baud Rate Generator Control
SBRLH1
0xB5
UART1 Baud Rate Generator High
SBRLL1
0xB4
UART1 Baud Rate Generator Low
SBUF1
0xD3
UART1 Data Buffer
SCON1
0xD2
UART1 Control
Table 9.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
Address
Description
Page